XW2Z-200J-B1 Omron, XW2Z-200J-B1 Datasheet - Page 383

• Manufacturer Part Number: XW2Z-200J-B1
• Description: CONNECTOR CABLE 2M
• Manufacturer: Omron

Specifications of XW2Z-200J-B1

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: XW2Z200JB1

FQM1 Memory Addresses
FQM1 memory addresses are set in Index Registers (IR0 or IR1) to indirectly address I/O memory. Normally,
FQM1 memory addresses are set into the Index Registers automatically when calling subroutines with
JSB(982).
Some instructions, such as FIND MAXIMUM (MAX(182)) and FIND MINIMUM (MIN(183)), output the results of
processing to an Index Register to indicate an FQM1 memory address.
There are also instructions for which Index Registers can be directly designated to use the FQM1 memory
addresses stored in them by other instructions. These instructions include DOUBLE MOVE (MOVL(498)),
some symbol comparison instructions (=L,<>L, <L, >L,<=L, and >=L), DOUBLE COMPARE (CMPL(060)),
DOUBLE INCREMENT BINARY (++L(591)), DOUBLE DECREMENT BINARY (– –L(593)), DOUBLE SIGNED
BINARY ADD WITHOUT CARRY (+L(401)), and DOUBLE SIGNED BINARY SUBTRACT WITHOUT CARRY
(–L(411)).
The FQM1 memory addresses all are continuous and the user must be aware of the order and boundaries of
the memory areas. As reference, the FQM1 memory addresses are provided in the next page.
Note Directly setting FQM1 memory addresses in the program should be avoided whenever possible. If FQM1
Memory Configuration
There are two classifications of the RAM memory (with capacitor backup) in the FQM1.
Parameter Areas: These areas contain Coordinator Module system setting data, such as the System Setup.
An illegal access error will occur if an attempt is made to access any of the parameter areas from an instruction
in the user program.
I/O Memory Areas: These are the areas that can be specified as operands in the instructions in user pro-
grams.
360
Auxiliary Area Allocations
memory addresses are set in the program, the program will be less compatible with new Modules for
which changes have been made to the layout of the memory.
Appendix D