UPD78F0034BGC-8BS-A Renesas Electronics America, UPD78F0034BGC-8BS-A Datasheet - Page 174
UPD78F0034BGC-8BS-A
Manufacturer Part Number
UPD78F0034BGC-8BS-A
Description
MCU 8-Bit 78K0 CISC 32KB Flash 2.5V/3.3V/5V 64-Pin LQFP
Manufacturer
Renesas Electronics America
Datasheet
1.UPD78F0034BGK-9ET-A.pdf
(605 pages)
Specifications of UPD78F0034BGC-8BS-A
Package
64LQFP
Family Name
78K0
Maximum Speed
12 MHz
Ram Size
1 KB
Program Memory Size
32 KB
Operating Supply Voltage
2.5|3.3|5 V
Data Bus Width
8 Bit
Program Memory Type
Flash
Number Of Programmable I/os
51
Interface Type
3-Wire/UART
On-chip Adc
8-chx10-bit
Operating Temperature
-40 to 85 °C
Number Of Timers
3
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(2) Oscillation stabilization time select register (OSTS)
172
Address: FFFAH
Symbol
OSTS
This register is used to select the oscillation stabilization time from when reset is effected or STOP mode is
released to when oscillation is stabilized.
OSTS is set by an 8-bit memory manipulation instruction.
RESET input sets OSTS to 04H. Thus, when releasing the STOP mode by RESET input, the time required to
release is 2
Note Expanded-specification products of PD780024A, 780034A Subseries only.
Caution
Remark f
X
17
The wait time when STOP mode is released does not include the time (“a” in the figure below)
from when STOP mode is released until the clock starts oscillation.
This also applies when RESET is input and an interrupt request is generated.
Figure 7-3. Format of Oscillation Stabilization Time Select Register (OSTS)
: Main system clock oscillation frequency
OSTS2
/f
X
.
7
0
0
0
0
0
1
After reset: 04H
Other than the above
OSTS1
Voltage waveform
of X1 pin
6
0
0
0
1
1
0
CHAPTER 7 CLOCK GENERATOR
OSTS0
R/W
5
0
0
1
0
1
0
User’s Manual U14046EJ5V0UD
STOP mode is released
Setting prohibited
2
2
2
2
2
12
14
15
16
17
/f
/f
/f
/f
/f
4
0
X
X
X
X
X
a
Selection of oscillation stabilization time
3
0
f
488 s
1.95 ms
3.91 ms
7.82 ms
15.6 ms
X
= 8.38 MHz
OSTS2
2
OSTS1
1
f
341 s
1.36 ms
2.73 ms
5.46 ms
10.9 ms
X
= 12 MHz
OSTS0
Note
0
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