UPD78F0034BGC-8BS-A Renesas Electronics America, UPD78F0034BGC-8BS-A Datasheet - Page 344

• Manufacturer Part Number: UPD78F0034BGC-8BS-A
• Description: MCU 8-Bit 78K0 CISC 32KB Flash 2.5V/3.3V/5V 64-Pin LQFP
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0034BGC-8BS-A

• Package: 64LQFP
• Family Name: 78K0
• Maximum Speed: 12 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 51
• Interface Type: 3-Wire/UART
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

(3) SO0 latch
(4) Wake-up controller
(5) Prescaler
(6) Serial clock counter
(7) Interrupt request signal generator
(8) Serial clock controller
(9) Serial clock wait controller
(10) ACK output circuit, stop condition detector, start condition detector, and ACK detector
(11) Data hold time correction circuit
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The SO0 latch is used to retain the SDA0 pin’s output level.
This circuit generates an interrupt request when the address received by this register matches the address value
set to slave address register 0 (SVA0) or when an extension code is received.
This selects the sampling clock to be used.
This counter counts the serial clocks that are output or input during transmit/receive operations and is used to
verify that 8-bit data was transmitted or received.
This circuit controls the generation of interrupt request signals (INTIIC0).
An I
• Falling of eighth or ninth clock of the serial clock (set by WTIM0 bit
• Interrupt request generated when a stop condition is detected (set by SPIE0 bit
Note WTIM0 bit: Bit 3 of IIC control register 0 (IICC0)
In master mode, this circuit generates the clock output via the SCL0 pin from a sampling clock.
This circuit controls the wait timing.
These circuits are used to output and detect various control signals.
This circuit generates the hold time for data corresponding to the falling edge of the serial clock.
2
C interrupt request is generated following either of two triggers.
SPIE0 bit: Bit 4 of IIC control register 0 (IICC0)
CHAPTER 18 SERIAL INTERFACE IIC0 ( PD780024AY, 780034AY SUBSERIES ONLY)
User’s Manual U14046EJ5V0UD
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