UPD78F0034BGC-8BS-A Renesas Electronics America, UPD78F0034BGC-8BS-A Datasheet - Page 290

• Manufacturer Part Number: UPD78F0034BGC-8BS-A
• Description: MCU 8-Bit 78K0 CISC 32KB Flash 2.5V/3.3V/5V 64-Pin LQFP
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0034BGC-8BS-A

• Package: 64LQFP
• Family Name: 78K0
• Maximum Speed: 12 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 51
• Interface Type: 3-Wire/UART
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

288
14.4.3 A/D converter operation mode
(ADS0) to start A/D conversion.
(1) A/D conversion by hardware start
A/D conversion
Select one analog input channel from among ANI0 to ANI7 using analog input channel specification register 0
A/D conversion can be started in either of the following two ways.
• Hardware start: Conversion is started by trigger input (rising edge, falling edge, or both rising and falling edges
• Software start: Conversion is started by setting A/D converter mode register 0 (ADM0).
When A/D conversion is complete, the interrupt request signal (INTAD0) is generated.
When bit 6 (TRG0) and bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) are set to 1, the A/D conversion
standby state is set. When the external trigger signal (ADTRG) is input, A/D conversion of the voltage applied
to the analog input pin specified by analog input channel specification register 0 (ADS0) starts.
Upon the end of A/D conversion, the conversion result is stored in A/D conversion result register 0 (ADCR0),
and the interrupt request signal (INTAD0) is generated. After one A/D conversion operation is started and
finished, the next conversion operation is not started until a new external trigger signal is input.
If ADS0 is rewritten during A/D conversion, the converter suspends A/D conversion and waits for a new external
trigger signal to be input. When the external trigger input signal is reinput, A/D conversion is carried out from
the beginning. If ADS0 is rewritten during A/D conversion standby, A/D conversion starts when the following
external trigger input signal is input.
If 1 is written to ADCS0 again during A/D conversion, the A/D conversion in progress is discontinued and a new
A/D conversion is started when the next external trigger input signal is input.
If 0 is written to ADCS0 during A/D conversion, the A/D conversion operation stops immediately.
Caution
Remarks 1. n = 0, 1, ......, 7
ADTRG
INTAD0
ADCR0
Figure 14-7. A/D Conversion by Hardware Start (When Falling Edge Is Specified)
2. m = 0, 1, ......, 7
When P03/INTP3/ADTRG is used as the external trigger input (ADTRG), specify the valid edge
using bits 1, 2 (EGA00, EGA01) of A/D converter mode register 0 (ADM0) and set the interrupt
mask flag (PMK3) to 1.
CHAPTER 14 10-BIT A/D CONVERTER ( PD780034A, 780034AY SUBSERIES)
ADM0 set
ADCS0 = 1, TRG0 = 1
enabled).
Standby
state
ANIn
User’s Manual U14046EJ5V0UD
ANIn
ANIn
Standby
state
ANIn
ANIn
Standby state
ANIn
ADS0 rewrite
Undefined
ANIm
ANIm
ANIm
ANIm
ANIm