UPD78F0034BGC-8BS-A Renesas Electronics America, UPD78F0034BGC-8BS-A Datasheet - Page 365

• Manufacturer Part Number: UPD78F0034BGC-8BS-A
• Description: MCU 8-Bit 78K0 CISC 32KB Flash 2.5V/3.3V/5V 64-Pin LQFP
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0034BGC-8BS-A

• Package: 64LQFP
• Family Name: 78K0
• Maximum Speed: 12 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 51
• Interface Type: 3-Wire/UART
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

18.5.12 Wake-up function
extension code have been received.
addresses do not match.
addresses are transmitted due to the possibility that an arbitration loss may change the master device (which has
output a start condition) to a slave device.
wake-up function, and this determines whether interrupt requests are enabled or disabled.
During address transmission
Read/write data after address transmission
During extension code transmission
Read/write data after extension code transmission
During data transmission
During ACK signal transfer period after data transmission
When restart condition is detected during data transfer
When stop condition is detected during data transfer
When data is at low level while attempting to output a
restart condition
When stop condition is detected while attempting to
output a restart condition
When data is at low level while attempting to output a
stop condition
When SCL0 is at low level while attempting to output a
restart condition
Notes 1. When WTIM0 (bit 3 of IIC control register 0 (IICC0)) = 1, an interrupt request occurs at the falling edge
Remark SPIE0: Bit 4 of IIC control register 0 (IICC0)
The I
This function makes processing more efficient by preventing unnecessary interrupt requests from occurring when
When a start condition is detected, wake-up standby mode is set. This wake-up standby mode is in effect while
However, when a stop condition is detected, bit 4 (SPIE0) of IIC control register 0 (IICC0) is set regardless of the
2
C bus slave function is a function that generates an interrupt request (INTIIC0) when a local address and
2. When there is a chance that arbitration will occur, set SPIE0 = 1 for master device operation.
CHAPTER 18 SERIAL INTERFACE IIC0 ( PD780024AY, 780034AY SUBSERIES ONLY)
of the ninth clock. When WTIM0 = 0 and the extension code’s slave address is received, an interrupt
request occurs at the falling edge of the eighth clock.
Table 18-4. Status During Arbitration and Interrupt Request Generation Timing
Status During Arbitration
User’s Manual U14046EJ5V0UD
At falling edge of eighth or ninth clock following byte transfer
When stop condition is output (when SPIE0 = 1)
At falling edge of eighth or ninth clock following byte transfer
When stop condition is output (when SPIE0 = 1)
At falling edge of eighth or ninth clock following byte transfer
Interrupt Request Generation Timing
Note 2
Note 2
Note 1
Note 1
Note 1
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