UPD78F0034BGC-8BS-A Renesas Electronics America, UPD78F0034BGC-8BS-A Datasheet - Page 604

• Manufacturer Part Number: UPD78F0034BGC-8BS-A
• Description: MCU 8-Bit 78K0 CISC 32KB Flash 2.5V/3.3V/5V 64-Pin LQFP
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0034BGC-8BS-A

• Package: 64LQFP
• Family Name: 78K0
• Maximum Speed: 12 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 51
• Interface Type: 3-Wire/UART
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

602
Third
edition
Edition
Addition of Figure 14-2 Format of A/D Conversion Result
Register 0 (ADCR0)
Modification of description in 14.2 (3) Sample & hold circuit, (4)
Voltage comparator, and addition of (10) ADTRG pin
Addition of Table 14-2 Sampling Time and A/D Conversion Start
Delay Time of A/D Converter
Deletion of 14.6 (4) Noise countermeasures (contents of deletion
are added to Figure 14-19 Example of Connecting Capacitor to
AV
Source Impedance Is High), and addition of (14) Input impedance
of ANI0 to ANI7 pins
Modification of Table 14-3 Resistances and Capacitances of
Equivalent Circuit (Reference Values)
Modification of Figure 16-1 Block Diagram of Serial Interface
UART0
Move of description of asynchronous serial interface status register
0 (ASIS0) in 16.3 Registers to Control Serial Interface UART0 to
16.2 Configuration of Serial Interface UART0
Addition of Caution in Figure 16-7 Error Tolerance (When k = 0 ),
Including Sampling Errors
Modification of Caution in Figure 16-10 Timing of Asynchronous
Serial Interface Receive Completion Interrupt Request
Addition of (1) Registers to be used and (3) Relationship
between main system clock and baud rate in 16.4.3 Infrared data
transfer mode
Addition of Table 16-6 Register Settings
Modification of Figure 17-1 Block Diagram of Serial Interface
SIO3n
Addition of Note 3 and Caution in Figures 17-2 Format of Serial
Operation Mode Register 30 (CSIM30) and 17-3 Format of Serial
Operation Mode Register 31 (CSIM31)
Addition of Table 17-2 Register Settings
Modification of Figure 18-1 Block Diagram of Serial Interface IIC0
Unification of 18.2 (1) IIC shift register 0 (IIC0) and (4) IIC shift
register 0 (IIC0) in 2nd edition, and (2) Slave address register 0
(SVA0) and (3) Slave address register 0 (SVA0) in 2nd edition
Addition of description to “Transfer lines” in Figure 18-16 Wait
Signal
Addition of description to Notes 1 and 2 in Table 18-2 INTIIC0
Timing and Wait Control
Modification of Figure 18-21 Master Operation Flowchart
Modification of 18.5.15 (2) Slave operation
Modification of (1) Start condition ~ address and (2) Data in
Figure 18-23 Example of Master to Slave Communication (When
9-Clock Wait Is Selected for Both Master and Slave)
Modification of Figure 18-24 Example of Slave to Master
Communication (When 9-Clock Wait Is Selected for Both Master
and Slave)
REF
Pin and Figure 14-21 Example of Connection If Signal
Revision from Previous Edition
APPENDIX E REVISION HISTORY
User’s Manual U14046EJ5V0UD
CHAPTER 14 10-BIT A/D CONVERTER
( PD780034A, 780034AY SUBSERIES)
CHAPTER 16 SERIAL INTERFACE
UART0
CHAPTER 17 SERIAL INTERFACES
SIO30 AND SIO31
CHAPTER 18 SERIAL INTERFACE IIC0
( PD780024AY, 780034AY SUBSERIES
ONLY)
Applied to:
(4/5)