UPD78F0034BGC-8BS-A Renesas Electronics America, UPD78F0034BGC-8BS-A Datasheet - Page 179
UPD78F0034BGC-8BS-A
Manufacturer Part Number
UPD78F0034BGC-8BS-A
Description
MCU 8-Bit 78K0 CISC 32KB Flash 2.5V/3.3V/5V 64-Pin LQFP
Manufacturer
Renesas Electronics America
Datasheet
1.UPD78F0034BGK-9ET-A.pdf
(605 pages)
Specifications of UPD78F0034BGC-8BS-A
Package
64LQFP
Family Name
78K0
Maximum Speed
12 MHz
Ram Size
1 KB
Program Memory Size
32 KB
Operating Supply Voltage
2.5|3.3|5 V
Data Bus Width
8 Bit
Program Memory Type
Flash
Number Of Programmable I/os
51
Interface Type
3-Wire/UART
On-chip Adc
8-chx10-bit
Operating Temperature
-40 to 85 °C
Number Of Timers
3
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7.4.3 When subsystem clock is not used
connect the XT1 and XT2 pins as follows.
when the main system clock stops. To minimize leakage current, the above internal feedback resistor can be removed
by setting bit 6 (FRC) of the processor clock control register (PCC). In this case also, connect the XT1 and XT2 pins
as described above.
If it is not necessary to use the subsystem clock for low power consumption operations and watch operations,
XT1: Connect directly to V
XT2: Leave open
In this state, however, some current may leak via the internal feedback resistor of the subsystem clock oscillator
Remark The feedback resistor is required to control the bias point of the oscillation waveform so that the bias
point is in the middle of the power supply voltage.
DD0
Figure 7-7. Subsystem Clock Feedback Resistor
or V
DD1
Feedback resistor
CHAPTER 7 CLOCK GENERATOR
XT1
User’s Manual U14046EJ5V0UD
P-ch
FRC
XT2
177
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