UPD78F0034BGC-8BS-A Renesas Electronics America, UPD78F0034BGC-8BS-A Datasheet - Page 319

• Manufacturer Part Number: UPD78F0034BGC-8BS-A
• Description: MCU 8-Bit 78K0 CISC 32KB Flash 2.5V/3.3V/5V 64-Pin LQFP
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0034BGC-8BS-A

• Package: 64LQFP
• Family Name: 78K0
• Maximum Speed: 12 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 51
• Interface Type: 3-Wire/UART
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

(d) Reception
Figure 16-10. Timing of Asynchronous Serial Interface Receive Completion Interrupt Request
RxD0 (input)
The receive operation performs level detection.
The receive operation is enabled when “1” is set to bit 6 (RXE0) of asynchronous serial interface mode
register 0 (ASIM0), and the input via the RxD0 pin is sampled.
The serial clock specified by baud rate generator control register 0 (BRGC0) is used to sample the RxD0
pin.
When the RxD0 pin goes low, the 5-bit counter of the baud rate generator begins counting and the start timing
signal for data sampling is output when half of the specified baud rate time has elapsed. If sampling the
RxD0 pin input at this start timing signal yields a low-level result, a start bit is recognized, after which the
5-bit counter is initialized and starts counting and data sampling begins. After the start bit is recognized,
the character data, parity bit, and one-bit stop bit are detected, at which point reception of one data frame
is completed.
Once reception of one data frame is completed, the receive data in the shift register is transferred to receive
buffer register 0 (RXB0) and INTSR0 (receive completion interrupt request) occurs.
If the RXE0 bit is reset (to 0) during a receive operation, the receive operation is stopped immediately. At
this time, the contents of RXB0 and ASIS0 do not change, nor does INTSR0 or INTSER0 (receive error
interrupt request) occur.
Figure 16-10 shows the timing of the asynchronous serial interface receive completion interrupt request.
Caution
INTSR0
If the receive operation is enabled with the RxD0 pin input at the low level, the receive
operation is immediately started. Make sure the RxD0 pin input is at the high level before
enabling the receive operation.
START
CHAPTER 16 SERIAL INTERFACE UART0
D0
User’s Manual U14046EJ5V0UD
D1
D2
D6
D7
Parity
STOP
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