UPD78F0034BGC-8BS-A Renesas Electronics America, UPD78F0034BGC-8BS-A Datasheet - Page 351

• Manufacturer Part Number: UPD78F0034BGC-8BS-A
• Description: MCU 8-Bit 78K0 CISC 32KB Flash 2.5V/3.3V/5V 64-Pin LQFP
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0034BGC-8BS-A

• Package: 64LQFP
• Family Name: 78K0
• Maximum Speed: 12 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 51
• Interface Type: 3-Wire/UART
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

Note If the wait status is cleared by setting bit 5 (WREL0) of IIC control register 0 (IICC0) to 1 at the ninth clock
Remark LREL0: Bit 6 of IIC control register 0 (IICC0)
Condition for clearing (COI0 = 0)
• When a start condition is detected
• When a stop condition is detected
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• When RESET is input
Condition for clearing (TRC0 = 0)
<Both master and slave>
• When a stop condition is detected
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• Cleared by WREL0 = 1
• When ALD0 changes from 0 to 1 (arbitration loss)
• When RESET is input
<Master>
• When “1” is output to the first byte’s LSB
<Slave>
• When a start condition is detected
• When “0” is input to the first byte’s LSB
<When not used for communication>
when bit 3 (TRC0) of IIC status register 0 (IICS0) is 1, TRC0 is cleared, and the SDA0 line goes into a
high-impedance state.
TRC0
(transfer direction specification bit)
(transfer direction specification bit)
COI0
CHAPTER 18 SERIAL INTERFACE IIC0 ( PD780024AY, 780034AY SUBSERIES ONLY)
0
1
0
1
IICE0:
Addresses do not match.
Addresses match.
Receive status (other than transmit status). The SDA0 line is set to high impedance.
Transmit status. The value in the SO0 latch is enabled for output to the SDA0 line (valid starting at
the falling edge of the first byte’s ninth clock).
Bit 7 of IIC control register 0 (IICC0)
Figure 18-6. Format of IIC Status Register 0 (IICS0) (2/3)
Note
(wait cancel)
User’s Manual U14046EJ5V0UD
Detection of transmit/receive status
Detection of matching addresses
Condition for setting (COI0 = 1)
• When the received address matches the local
Condition for setting (TRC0 = 1)
<Master>
• When a start condition is generated
<Slave>
• When “1” is input to the first byte’s LSB
address (slave address register 0 (SVA0))
(set at the rising edge of the eighth clock).
(transfer direction specification bit)
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