AT89C5132 Atmel Corporation, AT89C5132 Datasheet - Page 148
AT89C5132
Manufacturer Part Number
AT89C5132
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT89C5132.pdf
(3 pages)
2.AT89C5132.pdf
(182 pages)
3.AT89C5132.pdf
(38 pages)
4.AT89C5132.pdf
(33 pages)
Specifications of AT89C5132
Flash (kbytes)
64 Kbytes
Max. Operating Frequency
20 MHz
Cpu
8051-12C
Max I/o Pins
44
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Uart
1
Adc Channels
2
Adc Resolution (bits)
10
Adc Speed (ksps)
22.7
Sram (kbytes)
2.25
Self Program Memory
API
Operating Voltage (vcc)
2.7 to 3.6
Timers
2
Isp
UART/USB
Watchdog
Yes
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21.1.1
21.1.2
21.1.3
148
AT89C5132
Clock Generator
Channel Selection
Conversion Precision
Figure 21-2. Timing Diagram
The ADC clock is generated by division of the peripheral clock (see details in Section “X2 Fea-
ture”, page 12). The division factor is then given by ADCP4:0 bits in ADCLK register. Figure 21-
3 shows the ADC clock generator and its calculation formula
Figure 21-3. ADC Clock Generator and Symbol Caution:
Note:
The channel on which conversion is performed is selected by the ADCS bit in ADCON register
according to Table 30.
Table 30. ADC Channel Selection
The 10-bit precision conversion is achieved by stopping the CPU core activity during conversion
for limiting the digital noise induced by the core. This mode called the Pseudo-Idle mode
enabled by setting the ADIDL bit in ADCON register
Section "Conversion Launching", page 149), the CPU core is stopped until the end of the con-
1. In all cases, the ADC clock frequency may be higher than the maximum F
2. The ADCD value of 0 is equivalent to an ADCD value of 32.
ADEOC
ADSST
CLOCK
ADEN
reported in the Section “Analog to Digital Converter”, page 201.
PER
CLK
ADCS
T
0
1
÷ 2
SETUP
T
ADCD4:0
ADCLK
ADCLK
ADCclk
=
(3)
-------------------------
2 ADCD
PERclk
⋅
. Thus, when conversion is launched (see
T
ADC Clock
CONV
(1)
.
Channel
AIN1
AIN0
ADC Clock Symbol
CLOCK
ADCLK
ADC
4173E–USB–09/07
parameter
(1),(2)
is