AT89C5132 Atmel Corporation, AT89C5132 Datasheet - Page 26

• Manufacturer Part Number: AT89C5132
• Manufacturer: Atmel Corporation

Specifications of AT89C5132

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-12C
• Max I/o Pins: 44
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Uart: 1
• Adc Channels: 2
• Adc Resolution (bits): 10
• Adc Speed (ksps): 22.7
• Sram (kbytes): 2.25
• Self Program Memory: API
• Operating Voltage (vcc): 2.7 to 3.6
• Timers: 2
• Isp: UART/USB
• Watchdog: Yes

8.3
8.3.1
8.3.2
26
Dual Data Pointer
AT89C5132
Description
Application
The AT89C5132 implement a second data pointer for speeding up code execution and reducing
code size in case of intensive usage of external memory accesses.
DPTR0 and DPTR1 are seen by the CPU as DPTR and are accessed using the SFR addresses
83h and 84h that are the DPH and DPL addresses. The DPS bit in AUXR1 register (see
Table 15) is used to select whether DPTR is the data pointer 0 or the data pointer 1 (see
Figure 8-6).
Figure 8-6.
Software can take advantage of the additional data pointers to both increase speed and reduce
code size, for example, block operations (copy, compare, search …) are well served by using
one data pointer as a “source” pointer and the other one as a “destination” pointer.
Below is an example of block move implementation using the two pointers and coded in assem-
bler. The latest C compiler also takes advantage of this feature by providing enhanced algorithm
libraries.
The INC instruction is a short (2 Bytes) and fast (6 CPU clocks) way to manipulate the DPS bit in
the AUXR1 register. However, note that the INC instruction does not directly forces the DPS bit
to a particular state, but simply toggles it. In simple routines, such as the block move example,
only the fact that DPS is toggled in the proper sequence matters, not its actual value. In other
words, the block move routine works the same whether DPS is “0” or “1” on entry.
; ASCII block move using dual data pointers
; Modifies DPTR0, DPTR1, A and PSW
; Ends when encountering NULL character
; Note: DPS exits opposite of entry state unless an extra INC AUXR1 is added
AUXR1
move:
mv_loop: inc
end_move:
EQU
mov
inc
mov
movx
inc
inc
movx
inc
jnz
Dual Data Pointer Implementation
DPTR1
0A2h
DPTR,#SOURCE
AUXR1
DPTR,#DEST
AUXR1
A,@DPTR
DPTR
AUXR1
@DPTR,A
DPTR
mv_loop
DPTR0
DPH0
DPH1
DPL0
DPL1
; address of SOURCE
; switch data pointers
; address of DEST
; switch data pointers
; get a byte from SOURCE
; increment SOURCE address
; switch data pointers
; write the byte to DEST
; increment DEST address
; check for NULL terminator
DPS
0
1
0
1
AUXR1.0
DPH
DPL
DPTR
4173E–USB–09/07