AT89C5132 Atmel Corporation, AT89C5132 Datasheet - Page 48

• Manufacturer Part Number: AT89C5132
• Manufacturer: Atmel Corporation

Specifications of AT89C5132

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-12C
• Max I/o Pins: 44
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Uart: 1
• Adc Channels: 2
• Adc Resolution (bits): 10
• Adc Speed (ksps): 22.7
• Sram (kbytes): 2.25
• Self Program Memory: API
• Operating Voltage (vcc): 2.7 to 3.6
• Timers: 2
• Isp: UART/USB
• Watchdog: Yes

11.5
48
Registers
AT89C5132
Notes:
Table 18. PCON Register
PCON (S:87h) – Power Configuration Register
Reset Value = 00XX 0000b
Bit Number
SMOD1
–
5 - 4
7
7
6
3
2
1
0
A logic high on the RST pin clears PD bit in PCON register directly and
asynchronously. This starts the oscillator and restores the clock to the CPU and
peripherals. Program execution momentarily resumes with the instruction
immediately following the instruction that activated Power-down mode and may
continue for a number of clock cycles before the internal reset algorithm takes
control. Reset initializes the AT89C5132 and vectors the CPU to address 0000h.
1. During the time that execution resumes, the internal RAM cannot be accessed; however, it is
2. Exit from power-down by reset redefines all the SFRs, but does not affect the internal RAM
possible for the Port pins to be accessed. To avoid unexpected outputs at the Port pins, the
instruction immediately following the instruction that activated the Power-down mode should
not write to a Port pin or to the external RAM.
content.
Mnemonic
SMOD0
SMOD1
SMOD0
GF1
GF0
IDL
Bit
PD
6
-
Description
Serial Port Mode Bit 1
Set to select double baud rate in mode 1,2 or 3.
Serial Port Mode Bit 0
Set to select FE bit in SCON register.
Clear to select SM0 bit in SCON register.
Reserved
The value read from these bits is indeterminate. Do not set these bits.
General-Purpose Flag 1
One use is to indicate whether an interrupt occurred during normal operation or during
Idle mode.
General-Purpose Flag 0
One use is to indicate whether an interrupt occurred during normal operation or during
Idle mode.
Power-Down Mode Bit
Cleared by hardware when an interrupt or reset occurs.
Set to activate the Power-down mode.
If IDL and PD are both set, PD takes precedence.
Idle Mode Bit
Cleared by hardware when an interrupt or reset occurs.
Set to activate the Idle mode.
If IDL and PD are both set, PD takes precedence.
5
-
4
-
GF1
3
GF0
2
PD
1
4173E–USB–09/07
IDL
0