AT89C5132 Atmel Corporation, AT89C5132 Datasheet - Page 15

• Manufacturer Part Number: AT89C5132
• Manufacturer: Atmel Corporation

Specifications of AT89C5132

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-12C
• Max I/o Pins: 44
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Uart: 1
• Adc Channels: 2
• Adc Resolution (bits): 10
• Adc Speed (ksps): 22.7
• Sram (kbytes): 2.25
• Self Program Memory: API
• Operating Voltage (vcc): 2.7 to 3.6
• Timers: 2
• Isp: UART/USB
• Watchdog: Yes

4173E–USB–09/07
CKCON (S:8Fh) – Clock Control Register
Reset Value = 0000 000Xb
Table 2. PLLNDIV Register
PLLNDIV (S:EEh) – PLL N Divider Register
Reset Value = 0000 0000b
Bit Number
Bit Number
TWIX2
6-0
7
7
6
5
4
3
2
1
0
7
7
-
Mnemonic
Mnemonic
TWIX2
WDX2
WDX2
T1X2
T0X2
SIX2
N6:0
Bit
X2
N6
Bit
6
6
-
-
-
Description
Two-Wire Clock Control Bit
Set to select the oscillator clock divided by 2 as TWI clock input (X2 independent).
Clear to select the peripheral clock as TWI clock input (X2 dependent).
Watchdog Clock Control Bit
Set to select the oscillator clock divided by 2 as watchdog clock input (X2 independent).
Clear to select the peripheral clock as watchdog clock input (X2 dependent).
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Enhanced UART Clock (Mode 0 and 2) Control Bit
Set to select the oscillator clock divided by 2 as UART clock input (X2 independent).
Clear to select the peripheral clock as UART clock input (X2 dependent)..
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Timer 1 Clock Control Bit
Set to select the oscillator clock divided by two as Timer 1 clock input (X2 independent).
Clear to select the peripheral clock as Timer 1 clock input (X2 dependent).
Timer 0 Clock Control Bit
Set to select the oscillator clock divided by two as timer 0 clock input (X2 independent).
Clear to select the peripheral clock as timer 0 clock input (X2 dependent).
System Clock Control Bit
Clear to select 12 clock periods per machine cycle (STD mode, F
Set to select 6 clock periods per machine cycle (X2 mode, F
Description
Reserved
The value read from this bit is always 0. Do not set this bit.
PLL N Divider
7-bit N divider.
N5
5
5
-
SIX2
N4
4
4
N3
3
3
-
T1X2
N2
2
2
CPU
AT89C5132
T0X2
= F
N1
CPU
1
1
PER
= F
= F
PER
OSC
= F
).
N0
X2
0
0
OSC
/
2).
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