AT89C5132 Atmel Corporation, AT89C5132 Datasheet - Page 68
AT89C5132
Manufacturer Part Number
AT89C5132
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT89C5132.pdf
(3 pages)
2.AT89C5132.pdf
(182 pages)
3.AT89C5132.pdf
(38 pages)
4.AT89C5132.pdf
(33 pages)
Specifications of AT89C5132
Flash (kbytes)
64 Kbytes
Max. Operating Frequency
20 MHz
Cpu
8051-12C
Max I/o Pins
44
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Uart
1
Adc Channels
2
Adc Resolution (bits)
10
Adc Speed (ksps)
22.7
Sram (kbytes)
2.25
Self Program Memory
API
Operating Voltage (vcc)
2.7 to 3.6
Timers
2
Isp
UART/USB
Watchdog
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
15.1
15.1.1
68
Description
AT89C5132
Clock Controller
The USB device controller provides the hardware that the AT89C5132 need to interface a USB
link to data flow stored in a double port memory.
It requires a 48 MHz reference clock provided by the clock controller as detailed in Section
"Clock Controller", page 68. This clock is used to generate a 12 MHz Full Speed bit clock from
the received USB differential data flow and to transmit data according to full speed USB device
tolerance. Clock recovery is done by a Digital Phase Locked Loop (DPLL) block.
The Serial Interface Engine (SIE) block performs NRZI encoding and decoding, bit stuffing, CRC
generation and checking, and the serial-parallel data conversion.
The Universal Function Interface (UFI) controls the interface between the data flow and the Dual
Port RAM, but also the interface with the C51 core itself.
Figure 15-3 shows how to connect the AT89C5132 to the USB connector. D+ and D- pins are
connected through 2 termination resistors. A pull-up resistor is implemented on D+ to inform the
host of a full speed device connection. Value of these resistors is detailed in the section “DC
Characteristics”.
Figure 15-1. USB Device Controller Block Diagram
Figure 15-2. USB Connection
The USB controller clock is generated by division of the PLL clock. The division factor is given by
USBCD1:0 Bits in USBCLK register (see Table 70). Figure 15-3 shows the USB controller clock
CLOCK
USB
D+
D-
48 MHz
Buffer
USB
VBUS
GND
D+
D-
DPLL
VSS
To Power
Supply
SIE
VDD
12 MHz
R
FS
R
R
USB
USB
D+
D-
UFI
4173E–USB–09/07
To/From
C51 Core