AT89C5132 Atmel Corporation, AT89C5132 Datasheet - Page 61

• Manufacturer Part Number: AT89C5132
• Manufacturer: Atmel Corporation

Specifications of AT89C5132

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-12C
• Max I/o Pins: 44
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Uart: 1
• Adc Channels: 2
• Adc Resolution (bits): 10
• Adc Speed (ksps): 22.7
• Sram (kbytes): 2.25
• Self Program Memory: API
• Operating Voltage (vcc): 2.7 to 3.6
• Timers: 2
• Isp: UART/USB
• Watchdog: Yes

14.3
4173E–USB–09/07
Data Converter
Figure 14-2. Audio Clock Generator and Symbol
As soon as audio interface is enabled by setting AUDEN bit in AUDCON1 register, the master
clock generated by the PLL is output on the SCLK pin which is the DAC system clock. This clock
is output at 256 or 384 times the sampling frequency depending on the DAC capabilities. HLR bit
in AUDCON0 register must be set according to this rate for properly generating the audio bit
clock on the DCLK pin and the word selection clock on the DSEL pin. These clocks are not gen-
erated when no data is available at the data converter input.
For DAC compatibility, the bit clock frequency is programmable for outputting 16 bits or 32 bits
per channel using the DSIZ bit in AUDCON0 register (see Section "Data Converter", page 61),
and the word selection signal is programmable for outputting left channel on low or high level
according to POL bit in AUDCON0 register as shown in Figure 14-3.
Figure 14-3. DSEL Output Polarity
The data converter block converts the audio stream input from the 16-bit parallel format to a
serial format. For accepting all PCM formats and I
are used to shift the data output point. As shown in Figure 14-4, these bits allow MSB justifica-
tion by setting JUST4:0 = 00000, LSB justification by setting JUST4:0 = 10000, I
by setting JUST4:0 = 00001, and more than 16-bit LSB justification by filling the low significant
bits with logic 0.
Table 49. DAC Format Programing Examples
DAC Format
16-bit I
> 16-bit I
16-bit PCM
18-bit PCM LSB justified
20-bit PCM LSB justified
20-bit PCM MSB justified
2
S
2
S
CLOCK
PLL
POL = 0
POL = 1
AUCD4:0
AUDCLK
Left Channel
Left Channel
AUDclk
Audio Interface Clock
=
2
---------------------------
AUCD
S format, JUST4:0 bits in AUDCON0 register
PLLclk
+
Right Channel
Right Channel
POL
1
0
0
1
1
1
1
DSIZ
AT89C5132
0
1
0
1
1
1
Audio Clock Symbol
CLOCK
2
AUD
S Justification
JUST4:0
00001
00001
00000
00000
01110
01100
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