mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 132

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Cache Organization
4.8 Cache Organization
A four-way set associative cache is organized as four ways (levels). There are 128 sets in
the 8-Kbyte data cache with each line containing 16 bytes (4 longwords). The 16-Kbyte
instruction cache has 256 sets. Entire cache lines are loaded from memory by burst-mode
accesses that cache 4 longwords of data or instructions. All 4 longwords must be loaded for
the cache line to be valid.
Figure 4-3 shows data cache organization as well as terminology used.
A set is a group of four lines (one from each level, or way), corresponding to the same index
into the cache array.
4.8.1 Cache Line States: Invalid, Valid-Unmodified, and
As shown in Table 4-3, a data cache line can be invalid, valid-unmodified (often called
exclusive), or valid-modified. An instruction cache line can be valid or invalid.
A valid line can be explicitly invalidated by executing a CPUSHL instruction.
4-8
Set 0
Set 1
Set 126
Set 127
V
0
1
1
Where:
TAG—21-bit address tag
V—Valid bit for line
M—Modified bit for line (data cache only)
Valid-Modified
M
0
1
x
TAG
Invalid. Invalid lines are ignored during lookups.
Valid, unmodified. Cache line has valid data that matches system memory.
Valid, modified. Cache line contains most recent data, data at system memory location is stale.
Figure 4-3. Data Cache Organization and Line Format
Way 0
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Table 4-3. Valid and Modified Bit Settings
V M
Longword 0
MCF5407 User’s Manual
Way 1
Line
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Cache Line Format
Longword 1
Description
Way 2
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Longword 2
Longword 3
Way 3
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