mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 302

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

SDRAM Example
access can be a read or write. The important thing is that the address output of that access
needs the correct mode programming information on the correct address bits.
Figure 11-24 shows the
11.5 SDRAM Example
This example interfaces a 2M x 32-bit x 4 bank SDRAM component to a MCF5407
operating at 40 MHz. Table 11-32 lists design specifications for this example.
11.5.1 SDRAM Interface Configuration
To interface this component to the MCF5407 DRAM controller, use the connection table
that corresponds to a 32-bit port size with 8 columns (Table 11-26). Two pins select one of
four banks when the part is functional. Table 11-33 shows the proper hardware hook-up.
11-34
Speed grade (-8E)
10 rows, 8 columns
Two bank-select lines to access four internal banks
ACTV
Period between auto refresh and
ACTV
Precharge command to
Last data input to
Auto refresh period for 4096 rows (t
-to-read/write delay (t
command to precharge command (t
Figure 11-24. Mode Register Set (
Table 11-32. SDRAM Example Specifications
SRAS, SCAS
RAS[1] or [0]
MRS
PALL
DRAMW
D[31:0]
A[31:0]
CLKIN
command, which occurs in the first clock of the bus cycle.
command (t
Parameter
ACTV
RCD
command (t
)
MCF5407 User’s Manual
ACTV
RWL
REF
MRS
command (t
)
)
RAS
RP
)
)
RC
)
MRS
40 MHz (25-nS period)
20 nS (min.)
70 nS
48 nS (min.)
20 nS (min.)
1 bus clock (25 nS)
64 mS
) Command
Specification