mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 373

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Operation
The receiver detects the beginning of a break in the middle of a character if the break
persists through the next character time. If the break begins in the middle of a character, the
receiver places the damaged character in the Rx FIFO stack and sets the corresponding
USRn error bits and USRn[RxRDY]. Then, if the break lasts until the next character time,
the receiver places an all-zero character into the Rx FIFO and sets USRn[RB,RxRDY].
14.5.2.4 UART1 in UART Mode
After a hardware reset, UART1 is in UART mode and differs from UART0 only with
respect to receiver overrun, which is a function of Rx FIFO depth. UART0 has an effective
depth of 4 bytes counting the Rx shift register, whereas UART1 has an effective depth of
33 bytes counting the Rx shift register. As a result, an overrun error won’t occur in UART1
until 34 bytes are received without a CPU read from the Rx FIFO. In UART0, an overrun
error would occur after 5 bytes are received without a CPU read from the Rx FIFO. In all
other respects, UART1 in UART mode operates identically to UART0.
14.5.2.4.1 Receiver in Modem Mode (UART1)
After a hardware reset, UART1 is in UART mode. Modem modes are chosen by setting
MODCTL[MODE]. Other MODCTL fields should be initialized at the same time, as
described in Section 14.3.4, “Modem Control Register (MODCTL).” Set the Rx FIFO
threshold as described in Section 14.3.3, “Rx FIFO Threshold Register (RXLVL).”
The serial bit clock is always an input to UART1 in modem mode (on CTS). When
interfacing to an 8- or 16-bit CODEC, the frame sync is also an input to UART1 (on TIN1).
However when an AC ‘97 controller is used, UART1 provides the frame sync (on RTS).
Figure 14-31 on page 14-27 and Figure 14-32 on page 14-28 show timing diagrams for the
UART1-CODEC interfaces. Figure 14-33 shows an example timing diagram for the
UART1-AC ‘97 interface.
When an 8- or 16-bit CODEC is specified (MODCTL[MODE] = 01 or 10), UART1 starts
to receive a sample either at the rising edge of frame sync or 1 bit clock cycle after the rising
edge of frame sync, according to the value of MODCTL[DTS1]. The width of the frame
sync pulse makes no difference. MODCTL[SHDIR] controls whether the sample is shifted
in msb or lsb first. After the 8- or 16-bit sample is received, the receiver shift register shuts
off until the next frame sync occurs.
When an AC ‘97 controller is specified (MODCTL[MODE] = 11), UART1 starts to receive
time slot 1 data one bit-clock cycle after the rising edge of frame sync, regardless of the
MODCTL[DTS1] value. However, MODCTL[SHDIR] must be 0 because the shift order
must be msb first. Until the receiver detects the CODEC ready condition (a 1 in the first bit
of a new frame), no data is put into the Rx FIFO for that frame. When a CODEC ready
condition is detected, the receiver starts loading the Rx FIFO with the received time slot
samples and continues to do so until a 0 is received in the first bit of a new frame.
Chapter 14. UART Modules
14-31