mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 301

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

supports this sequence with the following procedure:
11.4.5.1 Mode Register Settings
It is possible to configure the operation of SDRAMs, namely their burst operation and CAS
latency, through the SDRAM component’s mode register. CAS latency is a function of the
speed of the SDRAM and the bus clock of the DRAM controller. The DRAM controller
operates at a CAS latency of 1, 2, or 3.
Although the MCF5407 DRAM controller supports bursting operations, it does not use the
bursting features of the SDRAMs. Because the MCF5407 can burst operand sizes of 1, 2,
4, or 16 bytes long, the concept of a fixed burst length in the SDRAMs mode register
becomes problematic. Therefore, the MCF5407 DRAM controller generates the burst
cycles rather than the SDRAM device. Because the MCF5407 generates a new address and
a
should be set either to a burst length of one or to not burst. This allows bursting to be
controlled by the MCF5407 instead.
The SDRAM mode register is written by setting the associated block’s DACR[IMRS].
First, the base address and mask registers must be set to the appropriate configuration to
allow the mode register to be set. Note that improperly set DMR mask bits may prevent
access to the mode register address. Thus, the user should determine the mapping of the
mode register address to the MCF5407 address bits to find out if an access is blocked. If the
DMR setting prohibits mode register access, the DMR should be reconfigured to enable the
access and then set to its necessary configuration after the
The associated CBM bits should also be initialized. After DACR[IMRS] is set, the next
access to the SDRAM address space generates the
address of the access should be selected to place the correct mode information on the
SDRAM address pins. The address is not multiplexed for the
READ
1. SDRAM control signals are reset to idle state. Wait the prescribed period after reset
2. Initialize the DCR, DACR, and DMR in their operational configuration. Do not yet
3. Issue a
4. Enable refresh (set DACR[RE]) and wait for at least 8 refreshes to occur.
5. Before issuing the
6. Issue the
before any action is taken on the SDRAMs. This is normally around 100 µs.
enable
SDRAM location. Wait the time (determined by t
modified to allow the
SDRAM. Note that mode register settings are driven on the SDRAM address bus, so
care must be taken to change DMR[BAM] if the mode register configuration does
not fall in the address range determined by the address mask bits. After the mode
register is set, DMR mask bits can be restored to their desired configuration.
or
WRITE
PALL
PALL
MRS
command for each transfer within the burst, the SDRAM mode register
or
command to the SDRAMs by setting DCR[IP] and accessing a
Chapter 11. Synchronous/Asynchronous DRAM Controller Module
command by setting DACR[IMRS] and accessing a location in the
REF
MRS
commands.
MRS
command, determine if the DMR mask bits need to be
to execute properly
MRS
RP
command to that SDRAM. The
MRS
) before any other execution.
command executes.
MRS
Synchronous Operation
command. The
11-33
MRS