mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 231

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Chapter 7
Phase-Locked Loop (PLL)
This chapter describes configuration and operation of the phase-locked loop (PLL) module.
It describes in detail the registers and signals that support the PLL implementation.
7.1 Overview
The basic features of the MCF5407 PLL implementation are as follows:
The PLL module has the following three modes of operation:
Figure 7-1 shows the frequency relationships of PLL module clock signals.
z
• The MCF5407 PLL is enhanced to support faster processor clock (PCLK)
• A buffered processor status clock (PSTCLK) is half the PCLK frequency, as
• Reset mode—In reset mode, the core/bus frequency ratio and other configuration
• Normal mode—During normal operations, the divide ratio is programmed at reset
• Reduced-power mode—In reduced-power mode, the high-speed processor core
frequencies than the MCF5307. It also offers a wider range of clock input ratios.
indicated in Figure 7-1. This signal is made available for system development.
information is sampled. At reset, the PLL asserts the reset out signal, RSTO.
and is clock-multiplied to provide the processor clock frequency. These frequencies
are described in the electrical specifications.”
clocks are turned off without losing the register contents so that the system can be
reenabled by an unmasked interrupt or reset.
DIVIDE[2:0]
CLKIN
RSTI
Figure 7-1. PLL Module Block Diagram
Chapter 7. Phase-Locked Loop (PLL)
PLL
CLKIN (to on-chip peripherals)
BCLKO
PCLK (to core)
RSTO
PSTCLK (= PCLK/2)
Debug Module
÷2
7-1