mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 151
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mcf5407
Manufacturer Part Number
mcf5407
Description
Mcf5407 Coldfire Integrated Microprocessor User
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MCF5407.pdf
(546 pages)
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; A 8K region was loaded into levels 0 and 1 of the 16-Kbyte instruction cache.
; lock it!
4.12 Cache Operation Summary
This section gives operational details for the cache and presents instruction and data
cache-line state diagrams.
4.12.1 Instruction Cache State Transitions
Because the instruction cache does not support writes, it supports fewer operations than the
data cache. As Figure 4-12 shows, an instruction cache line can be in one of two states, valid
or invalid. Modified state is not supported. Transitions are labeled with a capital letter
indicating the previous state and with a number indicating the specific case listed in
Table 4-6. These numbers correspond to the equivalent operations on data caches,
described in Section 4.12.2, “Data Cache State Transitions.”
Table 4-6 describes the instruction cache state transitions shown in Figure 4-12.
Read miss
Read hit
Write miss
Write hit
II5—ICINVA
II6—CPUSHL & IDPI
II7—CPUSHL & IDPI
Access
lea
subq.l
bne.b
move.l
movec
rts
II1 Read line from memory and update cache;
II2 Not possible
II3 Not possible
II4 Not possible
supply data to processor;
go to valid state.
Table 4-6. Instruction Cache Line State Transitions
Figure 4-12. Instruction Cache Line State Diagram
16(a0),a0
#1,d0
instCacheLoop
#0xa2088800,d0
d0,cacr
Invalid
V = 0
Invalid (V = 0)
Chapter 4. Local Memory
IV5—ICINVA
IV6—CPUSHL & IDPI
;instruction cache
;increment address to next line
;decrement loop counter
;if done, then exit, else continue
;set the instruction cache lock bit
;in the CACR
II1—CPU read miss
Current State
IV1 Read new line from memory and update cache;
IV2 Supply data to processor;
IV3 Not possible
IV4 Not possible
supply data to processor; stay in valid state.
stay in valid state.
V = 1
Valid
Valid (V = 1)
Cache Operation Summary
IV1—CPU read miss
IV2—CPU read hit
IV7—CPUSHL & IDPI
4-27
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