mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 370

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Operation
Figure 14-32 is an example timing diagram for the UART1-CODEC interface (msb first).
Figure 14-33 shows an example timing diagram for the UART1-AC ‘97 interface.
For more information about interfacing to an AC ‘97 controller, refer to the Audio
CODEC ‘97 Component Specification.
When interfaced to an 8- or 16-bit CODEC (MODCTL[MODE] = 01 or 10), UART1 starts
to send a sample either during the 1-bit clock cycle after the rising edge of frame sync,
according to the value of MODCTL[DTS1]. The width of the frame sync pulse makes no
difference. MODCTL[SHDIR] controls whether bits are shifted out msb or lsb first. After
the 8- or 16-bit sample is sent, zeros are sent until the next frame sync.
When interfacing to an AC ‘97 controller (MODCTL[MODE] = 11), UART1 starts to
transmit time slot 1 data one bit-clock cycle after the rising edge of frame sync, regardless
of the value of MODCTL[DTS1]. However, MODCTL[SHDIR] must be 0, because the
shift order must be msb first. UART1 divides the bit clock by 256 to generate a frame sync
pulse that is high for 16-bit clock cycles. The transmitter sends zeros until the receiver
detects the CODEC-ready condition (a 1 in the first bit of a new frame).
Because Rx data is sampled on the falling edge of the bit clock, for transmit purposes, the
frame has already started when the receiver detects a CODEC-ready condition. For this
reason, transmission starts at the next frame sync after the CODEC-ready condition is
detected. UART1 stops transmission at the end of the frame in which the first bit of the
received frame is detected low (CODEC not ready). During transmission, UART1 fills each
of the 13 time slots of the AC ‘97 frame with samples from the Tx FIFO.
14-28
CTS
RTS
RxD
TxD
TIN1
CTS
RxD
TxD
bit1 bit2
bit1 bit2
Frame Sync
Figure 14-32. 8-Bit CODEC Interface Timing (msb First)
Frame Sync
Figure 14-33. AC ‘97 Interface Timing
Slot 1
D7
D7
bit13
bit13
bit14 bit15
bit14 bit15
MCF5407 User’s Manual
D6
D6
bit16
bit16
Frame
D5
D5
20
20
Slot 2
Slot 2
bits
bits
20
20
Slot 3
Slot 3
bits
bits
D1
D1
D0
D0
20
20
Slot 13
Slot 13
bits
bits
Frame Sync
Slot 1
Slot 1