mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 353

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Bits
7
6
5
4
3
2
TxEMP Transmitter empty. For UART1, the function of TxEMP depends on which mode is used.
TxRDY
Name
RB
PE
OE
FE
Received break. The received break circuit detects breaks that originate in the middle of a received
character. However, a break in the middle of a character must persist until the end of the next
detected character time. RB is not used (and is always 0) in modem mode.
0 No break was received.
1 An all-zero character of the programmed length was received without a stop bit. RB is valid only
Framing error. FE is not used (and is always 0) in modem mode.
0 No framing error occurred.
1 No stop bit was detected when the corresponding data character in the FIFO was received. The
Parity error. Valid only if RxRDY = 1. PE is not used (and is always 0) in modem mode.
0 No parity error occurred.
1 If UMR1n[PM] = 0x (with parity or force parity), the corresponding character in the FIFO was
Overrun error. Indicates whether an overrun occurs. OE also functions this way for UART1 in
modem mode. (For purposes of overrun, FIFO full means all space in the FIFO is occupied; the Rx
FIFO threshold is irrelevant to overrun.)
0 No overrun occurred.
1 One or more characters in the received data stream have been lost. OE is set upon receipt of a
UART mode:
0 The transmitter buffer is not empty. Either a character is being shifted out, or the transmitter is
1 The transmitter has underrun (both the transmitter holding register and transmitter shift registers
Modem mode:
0 The transmitter does not have underrun as described above.
1 The transmitter has underrun, which means the number of bytes in the Tx FIFO is zero, the Tx
Transmitter ready.
UART0:
0 The CPU loaded the transmitter holding register or the transmitter is disabled.
1 The transmitter holding register is empty and ready for a character. TxRDY is set when a
UART1 (in UART or modem modes):
0 The transmitter FIFO is not empty, or the transmitter is disabled.
1 The transmitter FIFO is empty, as defined by TXLVL. TxRDY is set when the number of bytes in
when RxRDY = 1. Only a single FIFO position is occupied when a break is received. Further
entries to the FIFO are inhibited until RxD returns to the high state for at least one-half bit time,
which is equal to two successive edges of the UART clock.
stop-bit check occurs in the middle of the first stop-bit position. FE is valid only when RxRDY = 1.
received with incorrect parity. If UMR1n[PM] = 11 (multidrop), PE stores the received A/D bit.
new character when the FIFO is full and a character is already in the shift register waiting for an
empty FIFO position. When this occurs, the character in the receiver shift register and its break
detect, framing error status, and parity error, if any, are lost. OE is cleared by the
STATUS
disabled. The transmitter is enabled/disabled by programming UCRn[TC].
are empty). This bit is set after transmission of the last stop bit of a character if there are no
characters in the transmitter holding register awaiting transmission.
shift register is empty, and a frame sync occurs. In other words, the time has come to transmit a
new sample but no sample is available in the Tx shift register. Unlike UART mode, TxEMP high
indicates an error condition similar to the overrun condition (OE = 1), and as such it is now
cleared the same way as OE, by a
RESET TRANSMITTER
character is sent to the transmitter shift register and when the transmitter is first enabled. If the
transmitter is disabled, characters loaded into the transmitter holding register are not sent.
the Tx FIFO falls to, or below, the TXLVL value, due to the transfer of a sample (1 or 2 bytes) from
the Tx FIFO to the Tx shift register.
command in UCRn.
Table 14-7. USRn Field Descriptions
command in the UCRn.
Chapter 14. UART Modules
RESET ERROR STATUS
Description
command in the UCRn and not by a
Register Descriptions
RESET ERROR
14-11