mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 442

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Data Transfer Operation
18.4.7.3 Line Write Bus Cycles
Figure 18-16 shows a line access write with zero wait states. It begins like a basic write bus
cycle with data driven one clock after TS. The next pipelined burst data is driven a cycle
after the write data is registered (on the rising edge of S6). Each subsequent burst takes a
single cycle. Note that as with the line read example in Figure 18-12, AS and CSx remain
asserted throughout the burst transfer. This example shows the behavior of the address lines
for both internal and external termination. Note that with external termination, address
lines, like SIZ, TT, and TM, hold the same value for the entire transfer.
BE/BWEx, OE
External Termination
18-14
Internal Termination
TM[1:0], TT[1:0]
AS, CSx
SIZ[1:0]
TM[2:0]
D[31:0]
A[31:0]
TT[1:0]
OE, BE/BWE
CLKIN
Figure 18-16. Line Write Burst (2-1-1-1), Internal/External Termination
R/W
TIP
Figure 18-15. Line Read Burst-Inhibited, Fast, External Termination
TS
TA
R/W, TIP
AS, CSx
SIZ[1:0]
D[31:0]
A[31:0]
A[31:0]
CLKIN
TS
TA
S0
S1
A[3:2] = 00
S2 S3 S4 S5 S0 S1 S4 S5 S0 S1 S4 S5 S0 S1 S4 S5
Basic
S0
Line
Read
S1
MCF5407 User’s Manual
S2
S3
A[3:2] = 01
Write
Fast
Read
S4
S5
S6
A[3:2] = 10
Longword
Write
Fast
Read
S7
S8
Write
S9
A[3:2] = 11
Fast
Read
S10
Write
S11
S6
S7