mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 88
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mcf5407
Manufacturer Part Number
mcf5407
Description
Mcf5407 Coldfire Integrated Microprocessor User
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MCF5407.pdf
(546 pages)
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1
NOP
NOT
OR
ORI
PEA
PULSE
REMS
REMU
RTS
SATS
Scc
SUB
SUBA
SUBI
SUBQ
SUBX
SWAP
TAS
TRAP
TRAPF
TST
UNLK
WDDATA
Instruction
execution by setting CSR[UHE].
By default the HALT instruction is a supervisor-level instruction; however, it can be configured to allow user-mode
Instruction Set Summary
Table 2-9 describes supervisor-level instructions.
2-22
none
Dx
<ea>y,Dx
Dy,<ea>x
#<data>,Dx
<ea-3>y
none
<ea-1>,Dx
<ea-1>,Dx
none
Dx
Dx
<ea>y,Dx
Dy,<ea>x
<ea>y,Ax
#<data>,Dx
#<data>,<ea>x
Dy,Dx
Dx
<ea>x
#<vector>
None
#<data>
<ea>y
Ax
<ea>y
Operand Syntax
Table 2-8. User-Level Instruction Set Summary (Continued)
Unsized
.L
.L
.L
.L
Unsized
.L
.L
Unsized
.L
.B
.L
.L
.L
.L
.L
.L
.W
.B
Unsized
Unsized
.W
.L
.B,.W,.L
Unsized
.B,.W,.L
Operand Size
MCF5407 User’s Manual
Synchronize pipelines; PC + 2 → PC
~ Destination → destination
Source | destination → destination
Immediate data | destination → destination
SP – 4 → SP; Address of <ea> → (SP)
Set PST= 0x4
Dx/<ea>y → Dw {32-bit remainder}
Signed operation
Dx/<ea>y → Dw {32-bit remainder}
Unsigned operation
(SP) → PC; SP + 4 → SP
If CCR.V=1,
then if Dx[31] =0
then 0x80000000 → Dx
else 0x7FFFFFFF→ Dx
else Dx is unchanged
If condition true, then 1s destination;
Else 0s → destination
Destination – source → destination
Destination – source → destination
Destination – immediate data → destination
Destination – immediate data → destination
Destination – source – X → destination
MSW of Dx ←→ LSW of Dx
Set CCR; 1→ Bit 7 of <ea>x
SP – 4 → SP;PC → (SP);
SP – 2 → SP;SR → (SP);
SP – 2 → SP; format → (SP);
Vector address → PC
PC + 2 → PC
PC + 4 → PC
PC + 6 → PC
Set condition codes
Ax →SP; (SP) → Ax; SP + 4 → SP
<ea>y →DDATA port
Operation
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