mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 26

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

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Signal Relationship to CLKIN for Non-DRAM Access............................................. 18-2
Connections for External Memory Port Sizes ............................................................ 18-4
Chip-Select Module Output Timing Diagram ............................................................ 18-4
Data Transfer State Transition Diagram ..................................................................... 18-6
Read Cycle Flowchart................................................................................................. 18-7
Basic Read Bus Cycle................................................................................................. 18-8
Write Cycle Flowchart................................................................................................ 18-9
Basic Write Bus Cycle ................................................................................................ 18-9
Read Cycle with Fast Termination ........................................................................... 18-10
Write Cycle with Fast Termination........................................................................... 18-10
Back-to-Back Bus Cycles ......................................................................................... 18-11
Line Read Burst (2-1-1-1), External Termination .................................................... 18-12
Line Read Burst (2-1-1-1), Internal Termination ..................................................... 18-13
Line Read Burst (3-2-2-2), External Termination .................................................... 18-13
Line Read Burst-Inhibited, Fast, External Termination............................................ 18-14
Line Write Burst (2-1-1-1), Internal/External Termination...................................... 18-14
Line Write Burst (3-2-2-2) with One Wait State, Internal Termination ................... 18-15
Line Write Burst-Inhibited, Internal Termination .................................................... 18-15
Longword Read from an 8-Bit Port, External Termination...................................... 18-16
Longword Read from an 8-Bit Port, Internal Termination ....................................... 18-16
Example of a Misaligned Longword Transfer (32-Bit Port) .................................... 18-17
Example of a Misaligned Word Transfer (32-Bit Port) ............................................ 18-17
Interrupt-Acknowledge Cycle Flowchart ................................................................. 18-20
Basic No-Wait-State External Master Access .......................................................... 18-22
External Master Burst Line Access to 32-Bit Port.................................................... 18-24
MCF5407 Two-Wire Mode Bus Arbitration Interface............................................. 18-25
Two-Wire Bus Arbitration with Bus Request Asserted............................................ 18-26
Two-Wire Implicit and Explicit Bus Mastership...................................................... 18-27
MCF5407 Two-Wire Bus Arbitration Protocol State Diagram................................ 18-28
Three-Wire Implicit and Explicit Bus Mastership.................................................... 18-30
Three-Wire Bus Arbitration...................................................................................... 18-31
Three-Wire Bus Arbitration Protocol State Diagram ............................................... 18-32
Master Reset Timing................................................................................................. 18-34
Software Watchdog Reset Timing ............................................................................ 18-35
JTAG Test Logic Block Diagram ............................................................................... 19-2
JTAG TAP Controller State Machine......................................................................... 19-4
IDCODE Register ....................................................................................................... 19-6
Disabling JTAG in JTAG Mode ............................................................................... 19-11
Disabling JTAG in Debug Mode .............................................................................. 19-11
Supply Voltage Sequencing and Separation Cautions................................................ 20-3
Example Circuit to Control Supply Sequencing......................................................... 20-4
CLKIN-to-Core Clock Frequency Ranges.................................................................. 20-4
Clock Timing .............................................................................................................. 20-5
ILLUSTRATIONS
MCF5407 User’s Manual
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