mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 452

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

General Operation of External Master Transfers
Table 18-9 defines the cycles for Figure 18-25.
TT[1:0], TM[2:0]
18-24
C2–C3
Cycle
C1
C4
C5
BE/BWE
HOLDREQ
1
2
AS, BR
BG, BD
Depending on programming, these signals may or may not be driven by the processor.
These signals are driven by the processor for an external master transfer.
D[31:0]
SIZ[1:0]
CLKIN
A[31:0]
Table 18-9. Cycles for External Master Burst Line Access to 32-Bit Port
CS
TA
The external device is bus master and asserts HOLDREQ, indicating to the MCF5407 to hold all bus
requests. In other words, BD should not be asserted. The external master drives address, TS, R/W, TT[1:0],
TM[2:0], TIP, and SIZ[1:0] as inputs to the MCF5407. SIZ[1:0] inputs indicate a line transfer. The MCF5407
is not asserting BR.
The MCF5407 decodes the external device’s address and control signals to identify the proper chip-select
and byte-enable assertion. The external device negates TS in C2. Address and R/W are latched in the
MCF5407 on the rising edge of CLKIN in C2. After C2, the address and R/W are ignored for the rest of the
burst transfer.
On the falling edge of CLKIN, the MCF5407 asserts the appropriate chip select for the external device
access along with the appropriate byte enables.
On the rising edge of CLKIN, data is driven onto the bus by the device selected by CS. The MCF5407
asserts TA on the rising edge of CLKIN, indicating the first data transfer is complete.
R/W
TS
TIP
1
1
1
2
2
Figure 18-25. External Master Burst Line Access to 32-Bit Port
C1
C2
C3
MCF5407 User’s Manual
C4
C5
External Master
Definition
C6
C7
C8
C9
C10
C11