mcf5407 Freescale Semiconductor, Inc, mcf5407 Datasheet - Page 270

• Manufacturer Part Number: mcf5407
• Description: Mcf5407 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Overview
11.1.1 Definitions
The following terminology is used in this chapter:
11.1.2 Block Diagram and Major Components
The basic components of the DRAM controller are shown in Figure 11-1.
The DRAM controller’s major components, shown in Figure 11-1, are described as
follows:
11-2
Internal
A[31:0]
• A/SDRAM block—Any group of DRAM memories selected by one of the
• SDRAM—RAMs that operate like asynchronous DRAMs but with a synchronous
• SDRAM bank—An internal partition in an SDRAM device. For example, a 64-Mbit
• DRAM address and control registers (DACR0 and DACR1)—The DRAM
Bus
Figure 11-1. Asynchronous/Synchronous DRAM Controller Block Diagram
MCF5407 RAS[1:0] signals. Thus, the MCF5407 can support two independent
memory blocks. The base address of each block is programmed in the DRAM
address and control registers (DACR0 and DACR1).
clock, a pipelined, multiple-bank architecture, and faster speed.
SDRAM component might be configured as four 512K x 32 banks. Banks are
selected through the SDRAM component’s bank select lines.
controller consists of two configuration register units, one for each supported
memory block. DACR0 is accessed at MBAR + 0x0108; DACR1 is accessed at
0x010. The register information is passed on to the hit logic.
DRAM Address/Control Register 0
DRAM Address/Control Register 1
Memory Block 0 Hit Logic
Memory Block 1 Hit Logic
Page Hit
(DACR0)
(DACR1)
Logic
DRAM Controller Module
MCF5407 User’s Manual
Refresh Counter
Register (DCR)
DRAM Control
State Machine
Control Logic
Multiplexing
Address
and
A[31:0]
RAS[1:0]
CAS[3:0]
DRAMW
SCAS
SRAS
SCKE
These signals
are used for
SDRAM only