dp8344b National Semiconductor Corporation, dp8344b Datasheet - Page 10

• Manufacturer Part Number: dp8344b
• Description: Biphase Communications Processor?bcp
• Manufacturer: National Semiconductor Corporation

1 0 Communications Processor Introduction
Simultaneous access to both data and program memory
and instruction pipelining greatly enhance the speed per-
formance of the BCP making it well suited for real-time pro-
cessing The pipeline allows the next instruction to be re-
trieved from program memory while the current instruction is
being executed
1 3 TIMING INTRODUCTION
The timing of all CPU operations instruction execution and
memory access is related to the CPU clock This clock is
usually generated by a crystal and the internal oscillator
with optional divide by two circuitry The period of the result-
ing CPU clock is referred to as a T-state for example a
20 MHz CPU clock yields a 50 ns T-state Most CPU func-
tions such as arithmetic and logical operations shifts and
FIGURE 1-5 Effect of Memory Wait States on Timing
FIGURE 1-4 Memory Configuration
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rotates and register moves require only two T-states
Branching instructions and data memory accesses require
three to four T-states
Each memory system has a separate programmable num-
ber of wait states to allow the use of slower memory devic-
es Instruction memory wait states are inserted into all in-
structions as shown in Figure 1-5
overall speed of program execution Instruction memory
wait states can also apply when the Remote Interface is
loading a program into instruction memory Data memory
wait states are only inserted into data memory access in-
structions hence there is less degradation in overall pro-
gram execution Refer to the Timing section for detailed ex-
amples of all BCP instruction and data memory timing
(Continued)
TL F 9336 – C1
thus they affect the
TL F 9336 – C2