dp8344b National Semiconductor Corporation, dp8344b Datasheet - Page 85

• Manufacturer Part Number: dp8344b
• Description: Biphase Communications Processor?bcp
• Manufacturer: National Semiconductor Corporation

4-22 Until a Remote Write is initiated (RAE REM-WR true)
4 0 Remote Interface and Arbitration System (RIAS)
4 2 5 Latched Write
This mode executes a write without waiting the Remote
Processor XACK isn’t normally taken low The complete
flow chart for the Latched Write mode is shown in Figure
the state machine (RASM) loops in state RS
CPU needs to access Data Memory at this time (and LOCK
is high) it can still do so A local access is requested by the
Timing Control Unit asserting the Local Bus Request
(LCL-BREQ) signal A local bus grant will be given by RASM
if the buses are not being used (as is the case in RS
RASM will move into RS
RAE REM-WR is asserted
and therefore the RP is not waited The state machine will
loop in RS
RAE REM-WR is no longer true The external address and
data latches are typically latched on the trailing edge of
REM-WR A local bus request will still be serviced in this
state
Next RASM enters RS
vent overwrite of the external latches Since the RP has
completed its write cycle another write or read can happen
at any time Any Remote Read cycle (RAE REM-RD) or
Remote Write cycle (RAE REM-WR) occurring after the
state machine enters RS
cess initiated before or during this state must be completed
before RASM can move to RS
though no further local bus requests will be granted until
RASM enters the Termination Phase If the BCP CPU initi-
ates a Data Memory access after RS
Unit will be waited and the BCP CPU will remain in state T
until the RASM enters RS
RS
On the next clock the state machine enters RS
taken high WR-PEND continues to be asserted low in this
state and the data and instruction wait state counters i
and i
ly in DCR
and the Access Phase begins Any remote accesses now
occurring will take XACK low and wait the Remote Proces-
sor If the Remote Access is to IMEM and the high instruc-
tion byte flag is set (i e HIB
in RS
The state machine will move into one of several states on
the next clock depending on the state of CMD and
all the possible next states If CMD is high the access is to
es made by this write will not take effect until one T-state
after the completion of the present write
The five other next states all have CMD low and depend on
the Memory Select bits If MS1 – 0 is 10 or 11 the state
machine will enter either RS
bytes of the Program Counter respectively will be loaded
moves RASM into RS
state and A and AD continue to be tri-stated This allows the
Remote Processor to drive the Data Memory address and
data for the write Since DMEM is subject to wait states
RS
wait states have been inserted
MS1 – 0 WR-PEND remains low and LCL remains high in
MS1 – 0
RIC and the next state will be RS
RIC opens in this state Any remote access mode chang-
B
F4
IW
the A and AD buses go into TRI-STATE
E
is looped upon until all the programmed Data Memory
are loaded from DW2 – 0 and IW1 – 0 respective-
e
B
until the RP terminates its write cycle until
00 designates a Data Memory access and
The A and AD buses remain in TRI-STATE
F4
C
and WR-PEND is asserted to pre-
C
WRITE will be asserted low in this
H
will take XACK low A local ac-
F2
e
B
Half a T-state after entering
or RS
1) then IWR is asserted low
XACK is not taken low
on the next clock after
D
F1
Once RS
F3
C
The path from AD to
and the low or high
the Timing Control
A
D
E
is entered
If the BCP
and LCL is
A
)
DW
Wr
85
The last possible Memory Selection is Instruction Memory
pend on if RASM is expecting the low byte or high byte
Instruction words are accessed low byte then high byte and
RASM powers up expecting the low Instruction byte The
internal flag that keeps track of the next expected Instruc-
tion byte is called the High Instruction Byte flag (HIB) If HIB
is low the next state is RS
written into the holding register ILAT If HIB is high the high
instruction byte is moved to I15 – 8 and the value in ILAT is
moved to I7 – 0 At the same time IWR is asserted low and
the write to Instruction Memory is begun An IMEM access
like a DMEM access is subject to wait states and these
states will be looped on until all programmed instruction
memory wait states have been inserted
Note Resetting the BCP will reset HIB (i e HIB
All the RS
tests WAIT If WAIT is low then the state machine loops
back to RS
remains high and WR-PEND remains low in this state but
the actions specific to the RS
WRITE will no longer be asserted low)
The next CPU-CLK moves RASM into RS
the state machine LCL returns low but WR-PEND is still
low The A and AD buses remain in TRI-STATE for the first
half of RS
is initiated If the just completed access was to IMEM HIB
will be switched Also the PC will be incremented if the high
byte was written A local access will be granted if LCL-
BREQ is asserted in this state
If another Remote Write is pending the state machine takes
the path to RS
ing Remote Read will return to the RS
ered or Latched Read sections (not shown in Figure 4-22 )
of the state machine And if no Remote Access is pending
the machine will loop in RS
ed
In Figure 4-23 the BCP is executing the first of two Data
Memory writes when REM-WR goes low The BCP takes no
action until REM-WR goes back high latching the data and
making a remote access request The BCP responds to this
by taking WR-PEND low At the end of the first instruction
although the BCP begins its second write by taking ALE
high RASM now takes control of the bus and deasserts
LCL high at the end of T
this transfer to ensure that WRITE has been deasserted
high before the data bus is switched Timing Control Unit is
now waited inserting remote access wait states T
RASM takes over
The remote address is permitted one T-state to settle on the
BCP address bus before WRITE goes low WRITE then re-
turns high one T-state plus the programmed Data Memory
wait state T
time and one T-state later LCL is reasserted low transfer-
ring bus control back to the BCP
In this example REM-WR goes low again during the remote
write cycle which since WR-PEND is still low causes XACK
to go low to wait the Remote Processor Then LCL goes
low allowing the second data byte to be latched on the next
trailing edge of REM-WR One T-state later XACK and
WR-PEND go back high at the same time
MS1 – 0
Memory Select bits in RIC (i e
will also force HIB to zero This way the instruction word boundary
can be reset without resetting the BCP
e
F
H
F
01 The two possible next states for IMEM de-
states converge to a single decision box that
Wd
XACK will be taken low if a Remote Access
otherwise RASM will move on to RS
B
where that write will be processed A pend-
later having satisfied the memory access
(Continued)
1
F5
A
A one T-state delay is built into
and the low instruction byte is
until the next access is initiat-
F
MS1–0
states have ended (i e
A
e
e
H
in either the Buff-
01 pointing to IMEM)
0) Writing 01 to the
the last state in
G
Wr
LCL
as