dp8344b National Semiconductor Corporation, dp8344b Datasheet - Page 148

• Manufacturer Part Number: dp8344b
• Description: Biphase Communications Processor?bcp
• Manufacturer: National Semiconductor Corporation

6 0 Reference Section
MOVE Move Register
Syntax
MOVE Rs Rd
MOVE Rs mIr
MOVE Rs Ir
MOVE rs IZ
Affected Flags
None
Description
Moves the contents of the source register into the destina-
tion specified The source register operand Rs may specify
any active CPU register where as the source register oper-
and rs is limited to the active registers R0 – R15 The desti-
nation operand may specify either any active CPU register
Rd or data memory via one of the index register modes
tents of the index register Ir to the unsigned 8-bit value con-
tained in the currently active accumulator The immediate-
relative mode
adding the contents of the index register IZ to the unsigned
8-bit immediate value n
Example
The first example loads the Transmitter FIFO with a data
byte in register 20
The second example ‘‘pushes’’ the current accumulator’s
contents onto an external data stack which is pointed to by
the index register IX
The third example demonstrates the random access of a
data byte within a logical record contained in memory The
index register IY contains the base address of the logical
record
In the final example the 4th element of an Error Count table
is updated with a new value contained in the current accu-
mulator The index register IZ points to the 1st entry of the
table
mIr
Ir
EXX
MOVE R20 RTR
MOVE A IX
ADDA
MOVE R20 IY
MOVE A IZ
a
A forms its data memory address by adding the con-
Ir
a
0 1
R9 A
A
a
a
IZ
IZ
b
a
n
A
a
a
3
a
n
n
A
forms its data memory address by
register register
register indexed
register register-relative
limited register immediate-relative
The index register-relative mode
select main A alt B
Load the Transmitter FIFO
push accum to ext stack
calculate offset into record
update data byte in record
update 4th element of table
(Continued)
148
Instruction Format
MOVE Rs Rd
MOVE Rs Ir
MOVE rs Z
T-states
MOVE Rs Rd
MOVE Rs mIr
MOVE Rs Ir
MOVE rs IZ
Bus Timing
MOVE Rs Rd
MOVE Rs mIr
MOVE Rs Ir
MOVE rs IZ
Operation
MOVE Rs Rd
MOVE Rs mIr
MOVE Rs Ir
MOVE rs IZ
MOVE Rs mIr
1
15
1
15
0
15
Opcode
1
1
0
Opcode
0
1
0
0
1
1
Opcode
a
a
a
a
a
a
a
a
11
0
1
n
n
n
n
A
A
A
A
1
1
9
0
Figure 6-1
Figure 6-6
Figure 6-6
Figure 6-6
3
3
3
Rs
Rs
rs
2
Rs
0
x
x
x
x
n
Rd
1
data memory
Rd
data memory
data memory
6
v
00 IW
01 IX
10 IY
11 IZ
Ir
4
4
3
TL F 9336 – 10
Rs
Rs
rs
0
0
0