dp8344b National Semiconductor Corporation, dp8344b Datasheet - Page 47

• Manufacturer Part Number: dp8344b
• Description: Biphase Communications Processor?bcp
• Manufacturer: National Semiconductor Corporation

Figure 3-2(a)
3-3 through 3-5 The diagrams use a bit pattern drawing
ure 3-2
3 0 Transceiver
The transceiver has several modes of operation It can be
configured for single line half-duplex operation in which the
receiver is disabled while the transmitter is active Alterna-
tively both receiver and transmitter can be active at the
same time for multi-channel (such as repeater) or loopback
operation The transceiver has both internal and external
loopback capabilities facilitating testing of both the soft-
ware and external hardware At all times both transmitter
and receiver operate according to the same protocol defini-
tion
3 1 1 Protocols
In all protocols data is transmitted serially in discrete mes-
sages containing one or more frames each representing a
single word of information Biphase (Manchester II) encod-
ing is used in which the data stream is divided into discrete
time intervals (bit-times) denoted by a level transition in the
center of the bit-time For the IBM 3270 3299 and NSC
general purpose 8-bit protocols a mid-bit transition from low
to high represents a biphase ‘‘1’’ and a mid-bit transition
from high to low represents a biphase ‘‘0’’ For the 5250
protocol the definition of biphase logic levels is exactly re-
versed i e a biphase ‘‘1’’ is represented by a high to low
transition Depending on the bit sequence there may or
may not be a transition on the bit-time boundary The bi-
phase encoding of a simple bit sequence is illustrated in
Each transmission begins with a unique start sequence con-
sisting of 5 biphase encoded ‘‘1’s’’ (referred to as ‘‘line
quiesce pulses’’) followed by a 3 bit-time code violation and
the sync bit of the first frame Figure 3-2(b) The three bit-
time code violation does not conform to the rules of Man-
chester encoding and forms a unique recognition pattern for
bit time synchronization by the receiver logic The first bit of
any frame is the sync bit a biphase ‘‘1’’ The frame is then
formatted according to the requirements of the protocol If a
multi-frame message is being transmitted additional frames
are appended to the end of the first frame except for the
5250 protocol where there may be an optional number of
‘‘fill bits’’ (biphase ‘‘0’’) between each frame
Depending on the protocol when all data has been trans-
mitted the end of a message will be indicated either by the
transmission of an ending sequence or (for 5250) simply by
the cessation of transitions on the differential line Later
model 5250 equipment has incorporated a ‘‘line hold’’ at the
end of the message The line hold maintains the final differ-
ential state on the line for several bit times to eliminate
noise or reflections that could be interpreted as a continu-
ance of the message The ending sequence for all but 5250
protocols consists of a single biphase ‘‘0’’ followed by a low
to high transition on the bit-time boundary and two bit-times
with no transitions (two mini-code violation) Figure 3-2(c)
The various protocol framing formats are shown in Figures
convention which for clarity shows the bit-time boundaries
but not the biphase transitions in the center of the bit times
The timing relationship between the biphase encoded bit
stream and the bit pattern diagrams is consistent with Fig-
(Continued)
47
3-2(b) and (c) Each 12-bit frame begins with a sync bit (B1)
3 1 1 1 IBM 3270
The framing format of the IBM 3270 coax protocol is shown
in Figures 3-3(a) and (b) for both single and multi-frame
messages Each message begins with a starting sequence
and ends with an ending sequence as shown in Figures
followed by an 8-bit data byte (MSB first) a 2-bit control
field and the frame delimiter bit (B12) representing even
parity on the previous 11 bits The bit rate on the coax line is
2 3587 MHz
3 1 1 2 IBM 3299
Adding 3299 multiplexers to the 3270 environment requires
an address to be transmitted along with each message from
the controller to the multiplexer The IBM 3299 Terminal
Multiplexer protocol provides this capability by defining an
additional 8-bit frame as the first frame of every message
sent from the controller as shown in Figure 3-3(c) This
frame contains a 6-bit data field along with the normal sync
and word parity bits The protocol currently utilizes bits B2 –
B4 as an address field that directs the message through the
multiplexor hardware Following the address frame the rest
of the message follows standard 3270 convention The bit
rate 2 3587 MHz is the same as standard 3270
3 1 1 3 IBM 5250
The framing format of the IBM 5250 twinax protocol is
shown in Figure 3-4 for both single and multi-frame mes-
sages Each message begins with the starting sequence
shown in Figure 3-2(b) and ends with 3 fill bits (biphase
‘‘0’’) A 16-bit frame is employed consisting of a sync bit
(B15) an 8-bit data byte (B7 – B14) (LSB first) a 3-bit station
address field (B4 – B6) and the last bit (B3) representing
FIGURE 3-2 Biphase Encoding
(b) Starting Sequence
(a) Biphase Encoding
(c) Ending Sequence
TL F 9336 – 34
TL F 9336 – 36
TL F 9336 – 35