dp8344b National Semiconductor Corporation, dp8344b Datasheet - Page 17

• Manufacturer Part Number: dp8344b
• Description: Biphase Communications Processor?bcp
• Manufacturer: National Semiconductor Corporation

2 0 CPU Description
the data stack the next byte pushed will overwrite the first
after a write the BCP must execute one instruction before
reading the stack whose pointer was modified
The Data Stack register
the data stack This port is accessed like any other register
but a write to it will ‘‘push’’ a byte onto the stack and a read
from it will ‘‘pop’’ a byte from the stack The data stack
pointer is updated when a read or write of DS occurs
Information bits in the instruction address stack are not
mapped into the CPU’s register space and therefore are
not directly accessible A remote system running a monitor
program can access this information by forcing the BCP to
single-step through a return instruction and then reading the
program counter Since the stack pointers are writeable the
remote system can access any location (return address) in
the address stack to trace program flow and then restore
the stack pointer to its original position
2 1 2 Timer
The BCP has an internal 16-bit timer that can be used in a
variety of ways The timer counts independently of the CPU
eliminating the waste of valuable processor bandwidth The
timer can be used in a polled or interrupt driven configura-
tion for user software flexibility
The timer interfaces with the CPU via two registers TimeR
Low byte
the input output ports to the timer Writing to TRL and
time-out value into two holding registers The word stored in
the holding registers is the value that the timer will be load-
ISP can be read and written to like any other register but
TRH stores the low and high byte respectively of a 16-bit
TRL
and TimeR High byte
DS
is the input output port for
(Continued)
TRH
FIGURE 2-2 Timer Block Diagram
which form
17
ed with via TLD Also the timer will automatically reload
this word upon timing out Reading TRL and TRH pro-
vides access to the count down status of the timer
Control of timer operation is maintained via three bits in the
Auxiliary Control Register ACR
in ACR
rent value When low the timer stops and the timer interrupt
is cleared Timer Load TLD
control of the timer After writing the desired values into
word in the holding registers into the timer and initialize the
timer clock to zero in preparation to start counting Upon
completing the load operation
cleared Timer Clock Selection TCS bit 5 in ACR deter-
mines the clock frequency of the timer count down When
low the timer divides the CPU clock by sixteen to form the
clock for the down counter When TCS is high the timer
divides the CPU clock by two The input clock to the timer is
the CPU clock and should not be confused with the oscilla-
tor clock OCLK The rate of the CPU clock will be either
equal to OCLK or one-half of OCLK depending on the value
of bit 7 in the Device Control Register
When the timer reaches a count of zero the timer interrupt
is generated the Time Out flag TO (bit 7 in the Condition
Code Register CCR ) goes high and the timer reloads the
16-bit word stored in the holding registers to recycle through
a count down The timer interrupt and TO can be cleared
by either writing a one to TO in CCR or stopping the
timer by writing a zero to TST in ACR
of the timer is shown in Figure 2-2
TST allows the timer to start counting down from its cur-
TRL and TRH writing a one to TLD will load the 16-bit
is the start stop control bit Writing a one to
bit 6 in ACR
Timer STart TST bit 7
TLD
DCR
is automatically
A block diagram
TL F 9336 – D1
is the load