dp8344b National Semiconductor Corporation, dp8344b Datasheet - Page 80

• Manufacturer Part Number: dp8344b
• Description: Biphase Communications Processor?bcp
• Manufacturer: National Semiconductor Corporation

4 0 Remote Interface and Arbitration System (RIAS)
the last action of the remote access before moving to RS
is to switch HIB and increment the PC if the high byte was
written In RS
TRI-STATE for the first half of RS
access is initiated the next clock brings the state machine
back to RS
initiated
In Figure 4-19 the BCP is executing the first of two consec-
utive Slow Buffered Writes to Data Memory when REM-WR
goes low In response XACK goes low waiting the Remote
Processor At the end of the first instruction although the
BCP begins its second write by taking ALE high RASM now
Takes control of the bus and deasserts LCL high at the end
of T
that WRITE has been deasserted high before the data bus
is switched The Timing Control Unit is now waited inserting
remote access wait states T
The remote address is permitted one T-state to settle on the
BCP address bus before WRITE goes low XACK then re-
turns high one T-state plus the programmed Data Memory
wait state T
time The Remote Processor will respond by deasserting
REM-WR high to which the BCP in turn responds by deas-
serting WRITE high Following WRITE being deasserted
high the BCP waits till the end of the next T-state before
asserting LCL low again ensuring that the write cycle has
concluded before the bus is switched Control is then re-
turned to the Timing Control Unit and the local memory write
continues
4 2 4 Fast Buffered Write
The timing for the Fast Buffered Write mode is very similar
to the timing of the Latched Read The major difference is
the additional half clock that AD is active in the Latched
Read mode that is not present in the Fast Buffered Write
mode The Fast Buffered Write cycle ends after the data is
written and the termination doesn’t wait for the trailing edge
of REM-WR Therefore the Arbitration and Access Phases
of the Fast Buffered Write mode are the same as for the
Latched Read mode
The complete flow chart for the Fast Buffered Write mode is
shown in Figure 4-20 Until a Remote Write is initiated
(RAE REM-WR true) the state machine (RASM) loops in
state RS
1
A one T-state delay is built into this transfer to ensure
A1
A1
Wd
A3
If a Remote Write is initiated and
where it will loop until a Remote Access is
later having satisfied the memory access
LCL goes low while A and AD remain in
Wr
as RASM takes over
A3
If no new Remote
LOR
A3
80
is set high RASM will move to state RS
Remote Write is initiated while the buses have been granted
locally (i e Local Bus Grant
RS
BCP CPU needs to access Data Memory while in either RS
state (and LOCK is high) it can still do so A local access is
requested by the Timing Control Unit asserting the Local
Bus Request (LCL-BREQ) signal A local bus grant will be
given by RASM if the buses are not being used (as is the
case in the RS
XACK is taken low as soon as RAE REM-WR is true re-
gardless of an ongoing local access If LOR is low RASM
will move into RS
asserted and there is no local bus request No further local
bus requests will be granted until the BCP enters the Termi-
nation Phase If the BCP CPU initiates a Data Memory ac-
cess after RS
the BCP CPU will remain in state T
cess reaches the Termination Phase Half a T-state after
entering RS
On the next CPU-CLK RASM enters RS
high while XACK remains low The wait state counters i
and i
0 respectively in DCR
TRI-STATE and the Access Phase begins If the Remote
Access is to IMEM and the high instruction byte flag is set
(i e HIB
The state machine can move into one of several states de-
pending on the state of CMD and MS1 – 0 on the next
clock XACK and LCL in all the possible next states If CMD
is high the access is to RIC and the next state will be
RS
remote access mode changes made by this write will not
take effect until one T-state after the completion of the pres-
ent write
The five other next states all have CMD low and depend on
the Memory Select bits If MS1 – 0 is 10 or 11 the state
machine will enter either RS
bytes of the Program Counter respectively will be written
moves RASM into RS
LOR is set high or the buses are granted locally If the
MS1 – 0
A2
D1
DW
The state machine will loop in state RS
The path from AD to RIC opens in this state Any
are loaded in this state from IW1 – 0 and DW2 –
e
e
B
1) then IWR is asserted low in RS
A
the A and AD buses go into TRI-STATE
00 designates a Data Memory access and
A
the Timing Control Unit will be waited and
states)
B
on the next clock after RAE REM-WR is
(Continued)
D4
WRITE will be asserted in this
The A and AD buses remain in
D2
e
or RS
1) RASM will move to state
Wr
D3
until the remote ac-
and the low or high
C
A2
and LCL is taken
Likewise if a
A2
C
as long as
IW
A