dp8344b National Semiconductor Corporation, dp8344b Datasheet - Page 177

• Manufacturer Part Number: dp8344b
• Description: Biphase Communications Processor?bcp
• Manufacturer: National Semiconductor Corporation

Receiver
Control
(Continued)
Transmitter
Status
Receiver
Status
6 0 Reference Section
6 2 3 Bit Definition Tables (Continued)
6 2 3 2 Transceiver (Continued)
Table includes control and status bits only It does not include definitions of bit fields provided for the formatting (de-formatting)
data frames For further information see the Transceiver section
SLR
TA
TFE
TFF
ACK
DAV
DEME
LA
LTA
POLL
RA
RAR
RE
RFF
Bit
Select Line
Receiver
Transmitter Active TSR 6
Transmit FIFO
Empty
Transmit FIFO
Full
poll
ACKnowledge
Data AVailable
Data Error or
Message End
Line Active
Line Turn Around
POLL
Receiver Active
Received
Auto-Response
Receiver Error
Receive FIFO
Full
Name
(Continued)
Location Reset State
TCR 5
NCF 7
TSR 7
NCF 1
TSR 3
NCF 3
NCF 5
NCF 4
NCF 0
TSR 4
NCF 2
TSR 5
NCF 6
0
0
1
0
0
0
0
0
0
0
0
0
0
0
177
Selects the receiver input source
Reflects the state of TX-ACT indicating that data is being
transmitted Is not disabled by LOOP
Set high when the FIFO is empty Cleared by writing to
Set high when the FIFO is full RTR must not be written
when TFF is high
Set high when a 3270 poll ack command is decoded and
5250 and 8-bit modes and in the first frame of 3299 modes
Set high when valid data is available in RTR and TSR
Cleared by reading RTR or when an error is detected
In 3270 or 3299 modes asserted when a byte parity error is
detected In 5250 modes asserted when the 111 station
address is decoded and DAV is asserted Undefined in 8-bit
modes and first frame of 3299 modes
Indicates activity on the receiver input Set high on any
transition cleared after no input transitions are detected for
16 TCLK periods
Set high when an end of message is detected Cleared by
writing to RTR writing a ‘‘1’’ to LTA or by asserting
Set high when a 3270 Poll command is decoded and DAV is
asserted Cleared by reading RTR Undefined in 5250 and
8-bit modes and in the first frame of 3299 modes
Set high when a valid start sequence is received Cleared
when either an end of message or an error is detected
Set high when a 3270 Auto-Response message is decoded
and DAV is asserted Cleared by reading RTR Undefined
in 5250 and 8-bit modes and in the first frame of 3299 modes
Set high when an error is detected Cleared by reading ECR
or by asserting TRES
Set high when the receive FIFO contains 3 received words
Cleared by reading RTR
DAV is asserted Cleared by reading RTR Undefined in
TRES
RTR
SLR
0
1
Function
DATA-IN
On-Chip Analog
Line Receiver
Source