dp8344b National Semiconductor Corporation, dp8344b Datasheet - Page 31

• Manufacturer Part Number: dp8344b
• Description: Biphase Communications Processor?bcp
• Manufacturer: National Semiconductor Corporation

Figure 2-14 shows the relationship between CPU-CLK
2 0 CPU Description
ICLK and IA for a two T-state instruction The rising edge of
CPU-CLK generates ICLK at the start of T1 The next falling
edge of CPU-CLK increments the instruction address which
appears on IA ICLK falls one-half T-state later The instruc-
tion completes during T2 which ends with ICLK rising signi-
fying the beginning of the next instruction
The three T-state program control instruction is similar and
is shown in Figure 2-15 An additional T-state TX is added
between T1 and T2 ICLK rises at the beginning of T1 as
before but falls at the end of TX The next instruction ad-
dress is generated one-half T-state before the end of TX
and the instruction ends with T2
The three T-state data memory access instruction timing is
shown in Figure 2-16 Again TX is inserted between T1 and
T2 ICLK rises at the beginning of the instruction and falls at
the end of T1 The next instruction address appears on IA
one-half clock cycle before ICLK falls The address latch
enable output ALE rises halfway through T1 and falls half-
FIGURE 2-15 Three T-state Program Control Instruction
(Continued)
FIGURE 2-14 Two T-state Instruction
31
2-17 The read timing is the same as a write except one-half
way through TX The BCP has a 16-bit data memory ad-
dress bus and an 8-bit data bus The data bus is multiplexed
with the lower 8 bits of the address bus and ALE is used to
latch the lower 8 bits of the address during a data memory
access The upper 8 bits of the address become valid one-
half T-state after the beginning of T1 and go invalid one-half
T-state after the end of T2 The lower 8 bits of the address
become valid on the address-data bus AD when ALE rises
and goes invalid one-half T-state after ALE falls Figure 2-16
shows a write to data memory in which case AD switches
from address to data at the beginning of T2 The data is
held valid until one-half T-state after the end of T2 The
write strobe WRITE falls at the beginning of T2 and rises at
the end of T2 A read of data memory is shown in Figure
T-state after ALE falls AD goes into a high impedance state
allowing data to enter the BCP from data memory AD re-
turns to an active state at the end of T2 The read strobe
READ timing is identical to WRITE
TL F 9336 – D7
TL F 9336 – D8