dp8344b National Semiconductor Corporation, dp8344b Datasheet - Page 23

• Manufacturer Part Number: dp8344b
• Description: Biphase Communications Processor?bcp
• Manufacturer: National Semiconductor Corporation

2 0 CPU Description
Shift and Rotate Instructions
The shift and rotate instructions operate on any of the 8-bit
CPU registers The BCP supports shift left shift right and
rotate operations Table 2-8 lists the shift and rotate instruc-
tions
Comparison Instructions
The BCP utilizes two comparison instructions The CMP in-
struction performs a two’s complement subtraction between
a register and immediate data The BIT instruction tests se-
lected bits in a register by ANDing it with immediate data
Neither instruction stores its results only the ALU flags are
affected Table 2-9 lists both of the comparison instructions
Program Flow Instructions
The BCP has a wide array of program flow instructions un-
conditional jumps calls and returns conditional jumps
calls and returns relative or absolute instruction addressing
on jumps and calls a specialized register field decoding
Note ‘‘b’’
Note PC
SHL Rsd b
SHR Rsd b
ROT Rsd b
JMP
JMP
LJMP
LJMP
Syntax
Syntax
e
e
Program Counter contents initially points to instruction following jump
the number of bit shifts rotates to perform
n
Rs
nn
Ir
PC
PC
nn
Ir
Note
x
(Continued)
CMP rs n
BIT
x
a
a
Syntax
Instruction Operation
PC
n (sign extended)
Rs (sign extended)
PC
TABLE 2-10 Unconditional Jump Instructions
e
rs n
TABLE 2-8 Shift and Rotate Instructions
logical AND operation
TABLE 2-9 Comparison Instructions
Instruction Operation Addressing Mode
Instruction Operation
register
register
x
x
PC
PC
b
23
n
n
jump and software interrupt capabilities These instructions
redirect program flow by changing the Program Counter
The unconditional jump instructions support both relative in-
struction addressing the (JuMP instruction) and absolute
instruction addressing (the Long JuMP instruction) using
the following addressing modes Immediate Register Abso-
lute and Indexed Table 2-10 lists the unconditional jump
instructions and their variations
The conditional jump instructions support both relative in-
struction addressing and absolute instruction addressing us-
ing the Immediate and Absolute addressing modes The
conditional relative jump instruction tests flags in the Condi-
tion Code Register
Register
the conditional relative jump instruction see Table 2-11
Table 2-12 lists the various flags ‘‘f’’ that the conditional
JMP instruction can test and Table 2-13 lists the various
conditions ‘‘cc’’ that the Jcc instruction can test for Keep in
Operand Range
b
b
Limited Register
Limited Register
128
128
0 64k
0 64k
TSR
a
a
127
127
Two possible syntaxes are supported for
CCR
Immediate
Register
Absolute
Indexed
Addressing Mode
Addressing Mode
and the Transceiver Status
Register
Register
Register