dp8344b National Semiconductor Corporation, dp8344b Datasheet - Page 102

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dp8344b

Manufacturer Part Number
dp8344b
Description
Biphase Communications Processor?bcp
Manufacturer
National Semiconductor Corporation
Datasheet

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5 0 Device Specifications
Note 1 All parameters are individually tested and guaranteed Interpreting this data by numerically adding two or more parameters to create a new timing
specification may lead to invalid results
Note 2 Measurement thresholds at 2 5V
Note 3 The falling edge of ICLK occurs only after the next IA becomes valid The CLK-OUT cycle in which this occurs depends on the instruction being executed
and the number of programmed instruction wait states
Note 4 There is no relationship between X1 and X-TCLK X-TCLK is fully asynchronous
Note 5 External loading on pin X2 equal to 15 pF See Figure 5-6b for affect of X2 loading in non-crystal applications (i e an external oscillator driving X1)
t
t
t
t
t
t
t
T-X1
PD-X1-CO
PD-CO-ICLKr
PD-CO-ICLKf
T-XT
W-X1HL
W-XTHL
Symbol
ID
1
2
3
4
5
6
7
X1 Period (Note 2)
X1 to CLK-OUT (Note 2)
CLK-OUT Rising to ICLK Rising
CLK-OUT Rising to ICLK Falling (Note 3)
X-TCLK Period (Note 4)
X1 High and Low time Pulse Widths (Note 5)
XTCLK High and Low Time Pulse Widths
(Continued)
TABLE 5-6 Clock Timing (Note 1)
Parameter
FIGURE 5-6 Clock Timing
102
Formula
Min
TL F 9336 – 55
50
50
21
15
TL F 9336 – H8
Max
500
500
37
15
15
Units
ns
ns
ns
ns
ns
ns
ns

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