dp8344b National Semiconductor Corporation, dp8344b Datasheet - Page 167
dp8344b
Manufacturer Part Number
dp8344b
Description
Biphase Communications Processor?bcp
Manufacturer
National Semiconductor Corporation
Datasheet
1.DP8344B.pdf
(184 pages)
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6 0 Reference Section
ECR ERROR CODE REGISTER
OVF
PAR
IES
LMBT
RDIS
Alternate R4 with SEC high read only
rsv
7
rsv
Receiver oVerFlow
has processed 3 words and another complete
frame is received before the FIFO is read by the
CPU Cleared by reading ECR or by asserting
PARity error
word parity is detected in any receive frame
Cleared by reading
Invalid Ending Sequence
‘‘mini-code violation’’ is not correct during a 3270
3299 or 8-bit ending sequence Cleared by read-
ing ECR or by asserting TRES
Loss of Mid-Bit Transition
pected Manchester Code mid-bit transition does
not occur within the allowed window Cleared by
reading ECR or by asserting TRES
Receiver DISabled while active
transmitter is activated while receiver is active
without RPEN being asserted Cleared by reading
tion Section 3 2 Transceiver Functional Descrip-
tion
6
TRES
TRES
ECR or by asserting TRES Further informa-
rsv
5
OVF
4
PAR
Set when bad (odd) overall
3
ECR
Set when the receiver
(Continued)
IES
2
or by asserting
Set when the ex-
Set when the
LMBT RDIS
1
Set when
0
167
FBR FILL-BIT REGISTER
FB7 – 0
Alternate R3 read write
FB7
7
FB6
6
Fill Bits
tion Section 3 0 Transceiver
FB5
5
5250 fill-bit control Further informa-
FB4
4
FB3
3
FB2
2
FB1
1
FB0
0
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