dp8344b National Semiconductor Corporation, dp8344b Datasheet - Page 151
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dp8344b
Manufacturer Part Number
dp8344b
Description
Biphase Communications Processor?bcp
Manufacturer
National Semiconductor Corporation
Datasheet
1.DP8344B.pdf
(184 pages)
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Figure 6-1
6 0 Reference Section
RET Unconditional Return
Syntax
RET
Affected Flags
If rf
Description
Unconditionally returns control to the last instruction ad-
dress pushed onto the internal Address Stack by popping
that address into the Program Counter The unconditional
return instruction also has two optional operands g and rf
The value of g determines if the Global Interrupt Enable bit
Stack (g
is omitted then g
and rf determines if the ALU flags and register bank selec-
tions are left unchanged (rf
dress Stack (rf
assumed
Example
Return from an interrupt
Instruction Format
T-states
2
Bus Timing
Operation
Case g of
End case
If rf
End if
Address Stack
GIE is left unchanged (g
1
15
RET
0 leave GIE unaffected (default)
1 restore GIE from Address Stack
2 set GIE
3 clear GIE
restore ALU flags from Address Stack
restore register bank selection from Address Stack
e
e
0
1 then N Z C and V
1 then
g
e
1
1) set (g
1 1
rf
0
Opcode
e
x
1
e
1) If the rf operand is omitted then rf
0 is assumed The second optional oper-
PC
e
1
2) or cleared (g
1
Restore environment
e
1
e
0) restored from the Address
0) or restored from the Ad-
1
6
v
00 GIE not affected
01 Restore GIE
10 Set GIE
11 Clear GIE
g
(Continued)
e
3) If the g operand
rf
4
0
3
return
0
0
e
0 is
0
0
151
Figure 6-1
ROT Rotate
Syntax
ROT Rsd b
Affected Flags
N Z C
Description
Rotates the contents of the register Rsd b bits to the right
and places the result back into that register The bits that
are shifted out of the LSB are shifted back into the MSB
(and copied into the Carry flag) The value b may specify
from 0 to 7 bit rotates
Example
Add 3 to the Address Stack Pointer contained in the Internal
Stack Pointer register ISP
Instruction Format
T-states
2
Bus Timing
Operation
1
15
MOVE ISP R8
ROT
ADD
ROT
MOVE R8 ISP
1
0
R8 4
3 R8
R8 4
Opcode
0
1
0
1
register
get ISP
shift ASP to low order nibble
add 3 to ASP
shift ASP to high order nibble
store new ISP
0
R30
7
b
4
Rsd
TL F9336 – 12
0
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