peb22504 Infineon Technologies Corporation, peb22504 Datasheet - Page 31

• Manufacturer Part Number: peb22504
• Description: Quad Line Interface Unit For E1dt1dj1 Quadliu
• Manufacturer: Infineon Technologies Corporation

Figure 6
Each interrupt indication of register ISR0 and ISR1 can be masked selectively by setting
the corresponding bit in the mask registers IMR0 and IMR1. If the interrupt status bits
are masked, they neither generate an interrupt on pin INT nor are they visible in ISR(1:0).
The non-maskable Channel Interrupt Status (CIS) register serves as a pointer to pending
ISRs. After the QuadLIU™ has requested an interrupt by activating its INT pin, the CPU
should first read the CIS register to identify the requesting channel by bit GISx (Global
Interrupt Status bit of channel x) After that the corresponding interrupt status register
ISR(1:0) of the requesting channel should be examined. After reading the interrupt status
registers ISR(1:0), the pointer in CIS is cleared or updated if another interrupt requires
service.
If all pending interrupts are acknowledged by reading the ISRs, CIS is reset and pin INT
goes inactive.
Updating of ISR(1:0) and CIS is prohibited only during read access.
Masked Interrupts Visible in Status Registers
The CIS register indicates those channels with active interrupt indications.
An additional mode (“visible mode”) may be selected via bit LIM4.VIS. In this mode,
masked interrupt status bits neither generate an interrupt on pin INT nor are they visible
in CIS, but are displayed in the corresponding ISR(s) ISR(1:0).
This mode is useful when some interrupt status bits are to be polled in the individual
ISRs.
Data Sheet
CH4: IMR0 / IMR1
CH3: IMR0 / IMR1
Interrupt Status Registers
CH4: ISR0 / ISR1
CH3: ISR0 / ISR1
GIS4
GIS3
31
GIS2
GIS1
Channel Interrupt Status
Register (CIS)
CH1: ISR0 / ISR1
CH2: ISR0 / ISR1
CH1: IMR0 / IMR1
CH2: IMR0 / IMR1
Functional Description
QuadLIU V1.1
PEB 22504
2001-02
F0042