peb22504 Infineon Technologies Corporation, peb22504 Datasheet - Page 95
peb22504
Manufacturer Part Number
peb22504
Description
Quad Line Interface Unit For E1dt1dj1 Quadliu
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEB22504.pdf
(128 pages)
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SEC
Channel Interrupt Status Register (Read)
Address: 60
Value after reset: 00
CIS
This status register points to pending interrupts sourced by ISR1 and ISR0 of each
channel.
GIS4
GIS3
GIS2
GIS1
Data Sheet
H
7
One-Second Timer
The internal one-second timer has expired. The timer is derived from
clock RCLK, SCLKO, SCLKI or TCLK, depending on the monitor
block configuration. The selected clock source has to supply a
constant clock to ensure the correct function of the second timer.
Global interrupt status of register ISR1/0 of channel 4
Global interrupt status of register ISR1/0 of channel 3
Global interrupt status of register ISR1/0 of channel 2
Global interrupt status of register ISR1/0 of channel 1
H
95
GIS4
GIS3
GIS2
Register Description
QuadLIU V1.1
GIS1
0
PEB 22504
2001-02