peb22504 Infineon Technologies Corporation, peb22504 Datasheet - Page 91

• Manufacturer Part Number: peb22504
• Description: Quad Line Interface Unit For E1dt1dj1 Quadliu
• Manufacturer: Infineon Technologies Corporation

LLBDD
LLBAD
Line Status Register 1 (Read)
Addresses: 15
LSR1
TCS
XLS
Data Sheet
7
H
, 35
This bit is set if the LLB deactivate signal is detected and then
received over a period of more than 25 ms (E1) or 33.16 ms (T1) ,with
a bit error rate less than 10
error rate does not exceed 10
If automatic remote loop switching is disabled (LIM0.ARL = 0), any
change of this bit causes an LLBSC interrupt.
This bit is set if the LLB activate signal is detected and then received
over a period of more than 25 ms (E1) or 33.16 ms (T1), with a bit
error rate less than 10
rate does not exceed 10
If automatic remote loop switching is disabled (LIM0.ARL = 0), any
change of this bit causes an LLBSC interrupt.
Transmit Clock Status
Transmit Line Short
Line Loop-Back Deactivation Signal Detected
Line Loop-Back Activation Signal Detected
This bit is set if the transmit clock derived from TCLK failed to occur
for at least eight TCLK periods. The DCO reference is switched to
SYNC if not disabled by CMR.DCS. The transmit lines XL1/2 are
tristated automatically. With the first detected edge of the transmit
clock, this bit is cleared and tristating of XL1/2 is disabled.
Additionally, the interrupt status bit ISR1.LTC is set. MCLK must be
active because the reference frequency to detect a TCLK loss is
derived from this clock. The bit is also set during alarm simulation.
Significant only if the ternary line interface is selected by
LIM1.ECMIX = 0.
0 = Normal operation. No short is detected.
1 =
reaction of the short, pins XL1 and XL2 are automatically forced into
a high-impedance state if bit XPM2.DAXLT is reset. After 128
consecutive pulse periods, outputs XL1/2 are activated again and the
H
, 55
H
The XL1 and XL2 are shortened for at least three pulses. As a
, 75
H
-2
91
. The bit remains set as long as the bit error
-2
.
-2
. The bit remains set as long as the bit
-2
.
TCS
XLS
Register Description
QuadLIU V1.1
XLO
0
PEB 22504
2001-02