peb22504 Infineon Technologies Corporation, peb22504 Datasheet - Page 89

• Manufacturer Part Number: peb22504
• Description: Quad Line Interface Unit For E1dt1dj1 Quadliu
• Manufacturer: Infineon Technologies Corporation

6.4
Line Status Register 0 (Read)
Addresses: 14
LSR0
LOS
AIS
Data Sheet
LOS
Detailed Description of Status Registers
7
H
, 34
The loss-of-signal (LOS) detection offers the flexibility to fulfill allmost
all LOS requirements on the market (e.g. ANSI T1.403/231,
TR-WT-499, ITU-T G.775, ETS 300233).
Detection:
This bit is set when the incoming signal has no transitions in a time
interval of T consecutive pulses, where T is programmable via PCD
register.
Total count of consecutive pulses: 16 < T < 4096.
The receive signal level where “no transition” is declared is defined by
the programmed value of LIM2.RIL(2:0).
Recovery:
The bit is reset when the incoming signal has transitions with signal
levels
(LIM2.RIL(2:0)) for at least M pulse periods defined by register PCR
in the PCD time interval.
An interrupt status bit (ISR0.LOS) is set with the rising edge of this bit.
For additional recovery conditions according to ANSI T1.231, refer
also to register LIM5.LOSR(1:0).
The bit is also set during alarm simulation, and is reset if LIM0.SIM is
cleared and no alarm condition exists.
Alarm Indication Signal (Blue Alarm)
The AIS alarm is detected according to ITU-T G.775 and ANSI T1.231
standards.
E1 mode:
This bit is set when the incoming signal has fewer than three zeros in
each of two consecutive 512-bit periods. This bit is cleared when each
of two consecutive 512-bit periods contains three or more zeros.
Loss-of-Signal (Red Alarm)
H
AIS
, 54
H
, 74
greater
PDEN
H
EXZD
than
89
the
RLS
programmed
PRBSS
LLBAD
Register Description
receive
QuadLIU V1.1
LLBDD
0
PEB 22504
input
2001-02
level