peb22504 Infineon Technologies Corporation, peb22504 Datasheet - Page 96

• Manufacturer Part Number: peb22504
• Description: Quad Line Interface Unit For E1dt1dj1 Quadliu
• Manufacturer: Infineon Technologies Corporation

Code Violation Counter (Read)
Addresses CVCL: 19
Addresses CVCH: 1A
CVCL
CVCH
CV(15:0)
Data Sheet
CV15
CV7
7
7
Code Violations
E1 mode:
If the HDB3 or the CMI code is selected, the 16-bit counter is
incremented if violations of the HDB3 code are detected. The error
detection mode is determined by programming the bit LIM0.EXZE.
If simple AMI coding is enabled (LIM0.RC(1:0) = 00), all bipolar
violations are counted.
T1 mode:
If the B8ZS code (bit LIM0.RC(1:0) = 10, GCR2.PMODx = 1) is
selected, the 16-bit counter is incremented upon detection of
violations that are not due to zero substitution. If LIM0.EXZE is set,
excessive zero strings (more than seven contiguous zeros) are
detected and counted.
If simple AMI coding is enabled (LIM0.RC(1:0) = 00), all bipolar
violations are counted. If LIM0.EXZE is set, excessive zero strings
(more than 15 contiguous zeros) are detected and counted.
During alarm simulation, the counter is incremented every four bits
received up to its saturation.
Clearing and updating the counter is done according to bit LIM1.ECM.
If this bit is cleared, the error counter buffer is permanently updated.
For correct read access of the error counter, bit CMDR.DCVC has to
be set. With the rising edge of this bit, updating of the buffer is stopped
and the error counter is cleared. Bit CMDR.DCVC is reset
automatically with a read access to the error counter high byte.
If LIM1.ECM is set every second (interrupt ISR1.SEC), the error
counter is latched and then reset automatically. The latched error
counter state has to be read within the next second.
H
H
, 39
, 3A
H
H
, 59
, 5A
H
H
, 79
, 7A
H
H
96
Register Description
QuadLIU V1.1
CV0
CV8
0
0
PEB 22504
2001-02