peb22504 Infineon Technologies Corporation, peb22504 Datasheet - Page 49

• Manufacturer Part Number: peb22504
• Description: Quad Line Interface Unit For E1dt1dj1 Quadliu
• Manufacturer: Infineon Technologies Corporation

4.4
4.4.1
The QuadLIU™ offers two error counters. Each of them is 16 bits long. They record code
violations and PRBS errors. Both error counters are buffered. Updating of the buffer is
done in two modes:
• Every one-second interval
• On demand via handshake by writing to register CMDR
In the one-second-mode an internal/external one-second timer updates these buffers
and resets the counter to accumulating the error events. The error counter cannot
overflow. Error events occuring during reset don’t get lost.
4.4.2
A one-second timer interrupt can be generated per channel internally to indicate that the
enabled alarm status bits or the error counters have to be checked. The one-second
timer is part of the monitor block and is related to the selected clock source (RCLK,
SCLKO, SCLKI or TCLK).
4.4.3
The QuadLIU™ has the ability to generate and monitor a 2
maximum zero restriction according to ITU-T O.151 and AT&T TR62411. The generated
PRBS pattern is transmitted directly or inverted.
The PRBS monitor senses the PRBS pattern in the receive or transmit data stream.
Synchronization is done with inverted and non-inverted PRBS patterns. The current
synchronization status is reported in status and interrupt status registers. Data streams
consisting of continuous ones or zeros also lead to the indication of synchronous state.
Each PRBS bit error increments the PRBS error counter (BECL/H). Synchronization is
reached within 400 ms at a probability of 99.9 % in the presence of a bit error rate
of
Data Sheet
10
-1
.
Maintenance Functions
Error Counter
One-Second Timer
Pseudo-Random Bit Sequence Generation and Monitor
49
15
-1 or 2
Interface Description
QuadLIU V1.1
20
-1 PRBS with
PEB 22504
2001-02