peb22504 Infineon Technologies Corporation, peb22504 Datasheet - Page 83

• Manufacturer Part Number: peb22504
• Description: Quad Line Interface Unit For E1dt1dj1 Quadliu
• Manufacturer: Infineon Technologies Corporation

Command Register (Read/Write)
Addresses: 13
Value after reset: 00
CMDR
RES
IBV
IPE
CEB
DBEC
DCVC
Data Sheet
RES
7
H
, 33
Note: The maximum time between writing to the CMDR register and
The receive and the transmit line interface (except the clock and data
recovery unit DPLL) are reset. The contents of the control registers is
not deleted.
Insert Bipolar Violations
Setting this bit forces a bipolar violation in the transmit data stream.
Violations are inserted at the next possible position. Ones preceded
by two or more zeros are not converted into violations.
Example (V = inserted violation):
001000010100 is converted to 001000010V00
Insert PRBS Error
Setting this bit forces a PRBS error in the outgoing data stream (if
PRBS transmission is enabled).
Center Elastic Buffer
Setting this bit forces the delay through the elastic buffer to half of the
current buffer size (LOOP.BS1/0).
This bit is only valid if LIM1.ECM is cleared. It must be set before
reading the error counter. This bit is reset automatically if the
corresponding error counter high byte has been read. With the rising
edge of this bit the error counter is latched and then cleared.
See bit DBEC.
Reset Receiver and Transmitter
Disable Pseudo-Random Binary Sequence Error Counter
Disable Code Violation Counter
H
H
, 53
H
the execution of the command takes 2.5 periods of the current
line data rate. Register bits are set by software and reset by
hardware automatically after the required operation has been
completed. Register bits in CMDR cannot be reset by software.
, 73
H
IBV
83
IPE
CEB
DBEC
Register Description
QuadLIU V1.1
DCVC
0
PEB 22504
2001-02