peb22504 Infineon Technologies Corporation, peb22504 Datasheet - Page 92

• Manufacturer Part Number: peb22504
• Description: Quad Line Interface Unit For E1dt1dj1 Quadliu
• Manufacturer: Infineon Technologies Corporation

XLO
Receive Equalizer Status (Read)
Addresses: 16
RES
EV(1:0)
RES(4:0)
Data Sheet
EV1
7
H
, 36
Transmit Line Open
0 =
1 =
Equalizer Status Valid
These bits inform the user about the current state of the receive
equalization network. Only valid if LIM1.EQON is set.
00 = Equalizer status not valid, still adapting
01 = Equalizer status valid
10 = Equalizer status not valid
11 = Equalizer status valid but high noise floor
These bits display current line attenuation status in steps of
approximately 1.4 (T1 J1) 1.7 (E1) dB. Only valid if bits EV(1:0) = 01.
Accuracy: ± 2 digits, based on temperature influence and noise
amplitude variations.
00000 = Minimum gain (0 dB)
...
11001 = Maximum equalizer gain
Receive Equalizer Status
internal transmit current limiter is checked. If a short between XL1/2
is still active, outputs XL1/2 are in high-impedance state again. When
the short disappears, pins XL1/2 are activated automatically and this
bit is reset. With any change of this bit, an interrupt ISR0.XLSC is
generated. If XPM2.XLT is set, this bit is frozen.
Note: For maximum receiver sensitivity set bits LIM2.RIL(2:0) = 110
H
EV0
, 56
Normal operation
This bit is set if at least 32 consecutive zeros were sent via pins
XL1/XL2. This bit is reset with the first transmitted pulse. An
interrupt ISR0.XLSC is set with the rising edge of this bit. If
XPM2.XLT is set, this bit is frozen.
H
, 76
H
RES4
92
RES3
RES2
RES1
Register Description
QuadLIU V1.1
RES0
0
PEB 22504
2001-02