peb22504 Infineon Technologies Corporation, peb22504 Datasheet - Page 97

• Manufacturer Part Number: peb22504
• Description: Quad Line Interface Unit For E1dt1dj1 Quadliu
• Manufacturer: Infineon Technologies Corporation

PRBS Bit Error Counter (Read)
Addresses CVCL: 1B
Addresses CVCH: 1C
BECL
BECH
BEC(15:0)
Version Status Register (Read)
Address: 7F
VSTR
VN(7:0)
Data Sheet
BEC15
BEC7
VN7
H
7
7
7
PRBS Bit Error Counter
This 16-bit counter is incremented with every received PRBS bit error
in the PRBS synchronous state LSR0.PRBSS = 1.
Clearing and updating of the counter is done according to bit
LIM1.ECM. If this bit is cleared, the error counter buffer is
permanently updated. For correct read access of the error counter bit
CMDR.DBEC has to be set. With the rising edge of this bit, updating
the buffer is stopped and the error counter is cleared. Bit
CMDR.DBEC is reset automatically with a read access to the error
counter high byte.
If LIM1.ECM is set every second (interrupt ISR1.SEC) the error
counter is latched and then cleared automatically. The latched error
counter state has to be read within the next second.
00
Version Number of the Chip
VN6
H
H
H
, 3B
=Version 1.1
, 3C
H
H
, 5B
, 5C
VN5
H
H
, 7B
, 7C
VN4
H
H
97
VN3
VN2
VN1
Register Description
QuadLIU V1.1
BEC0
BEC8
VN0
0
0
0
PEB 22504
2001-02