peb22504 Infineon Technologies Corporation, peb22504 Datasheet - Page 82

• Manufacturer Part Number: peb22504
• Description: Quad Line Interface Unit For E1dt1dj1 Quadliu
• Manufacturer: Infineon Technologies Corporation

Example:
Transmit LLB/IBL activate Code = 00001
Register setting LCR1: xx00xx01
Register setting LCR3: xxx00001
Interrupt Mask Register (0:1) (Read/Write)
Addresses IMR0: 11
Addresses IMR1: 12
Value after reset: FF
IMR0
IMR1
IMR(0:1)
Data Sheet
LLBSCM XLSCM
7
default setting is (000)00001 (5-bit mode is default in LCR1). This
generates the standard activate code "00001".
Interrupt Mask Register
Each interrupt source can generate an interrupt signal on port INT. A
"1" in a bit position of IMR(0:1) sets the mask active for the interrupt
status in ISR(0:1). Masked interrupt statuses neither generate a
signal on INT, nor are they visible in register CIS. Moreover, they are
– not displayed in the ISR if bit LIM4.VIS is cleared
– displayed in the ISR if bit LIM4.VIS is set
Note: After reset, all interrupts are disabled.
H
H
H
, 31
, 32
, FF
See register ISR0/1 for detailed description of bit functions.
H
H
H
PRBSSCM
, 51
, 52
H
H
, 71
, 72
H
H
SLNM
82
SLPM
PDENM
LTCM
AISM
Register Description
QuadLIU V1.1
SECM
LOSM
0
PEB 22504
2001-02